Patents by Inventor Chooi Pei Lim
Chooi Pei Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230049681Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.Type: ApplicationFiled: October 25, 2022Publication date: February 16, 2023Applicant: Intel CorporationInventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
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Patent number: 11500412Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.Type: GrantFiled: March 28, 2019Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
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Publication number: 20220014182Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a data strobe generation circuit with a first via configuration and/or a data buffer circuit with a second configuration.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Inventors: Chooi Pei Lim, Eah Loon Alan Chuah, Eng Huat LEE, Marian Serban, Marian Cretu
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Patent number: 10530367Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.Type: GrantFiled: December 28, 2018Date of Patent: January 7, 2020Assignee: Intel CorporationInventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
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Publication number: 20190227590Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.Type: ApplicationFiled: March 28, 2019Publication date: July 25, 2019Applicant: Intel CorporationInventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
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Publication number: 20190140647Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
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Patent number: 9577649Abstract: Integrated circuits with clock distribution circuitry are provided. The clock distribution circuitry may include a clock source, a clock distribution network, a frequency encoder placed at the output of the clock source, and one or more frequency decoders placed at the destinations of the clock distribution network. The frequency encoder can be used to obtain calibrated delay settings proportional to a reference clock generated by the clock source. Each frequency decoder can be placed in a closed loop configuration and can use the calibrated delay settings to locally self-generate a recovered clock at the destination during a locked state. During the locked state, clock buffers in the clock distribution network can be powered down to save power.Type: GrantFiled: March 14, 2016Date of Patent: February 21, 2017Assignee: Altera CorporationInventors: Boon Pin Liong, Chooi Pei Lim
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Patent number: 9430433Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.Type: GrantFiled: February 7, 2014Date of Patent: August 30, 2016Assignee: Altera CorporationInventors: Keong Hong Oh, Yee Liang Tan, Siang Poh Loh, Chooi Pei Lim
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Patent number: 9401281Abstract: A mask set is described. In one implementation, the mask set includes: a first plurality of base layer masks, where each base layer mask of the first plurality of base layer masks includes a plurality of base layer tiles of a first tile size; a first plurality of top layer masks, where each top layer mask of the first plurality of top layer masks includes a plurality of first top layer tiles of the first tile size; and a second plurality of top layer masks, where each top layer mask of the second plurality of top layer masks includes a plurality of second top layer tiles of a second tile size; where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described.Type: GrantFiled: May 19, 2014Date of Patent: July 26, 2016Assignee: Altera CorporationInventors: Jordan Plofsky, Chooi Pei Lim, Danny Biran, Francis Man-Chit Chow
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Patent number: 9236864Abstract: An integrated circuit (IC) is provided where the IC includes a first die, a second die stacked above the first die, and a plurality of die-to-die interconnects coupling the first die to the second die, where the plurality of die-to-die interconnects includes at least one redundancy die-to-die interconnect. In one implementation, the plurality of die-to-die interconnects includes a plurality of pre-designated die-to-die interconnects, where if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.Type: GrantFiled: January 17, 2012Date of Patent: January 12, 2016Assignee: Altera CorporationInventors: Siang Poh Loh, Chooi Pei Lim
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Patent number: 9225335Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.Type: GrantFiled: November 19, 2013Date of Patent: December 29, 2015Assignee: ALTERA CORPORATIONInventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
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Patent number: 8793547Abstract: Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms are provided for determining not only the presence of a defect in a given set of interfaces of an integrated circuit, but the particular interface at which a defect may exist.Type: GrantFiled: January 2, 2013Date of Patent: July 29, 2014Assignee: Altera CorporationInventors: Siang Poh Loh, Chooi Pei Lim
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Patent number: 8786308Abstract: Integrated circuit packages with a signal routing control through a given direction are disclosed. A disclosed integrated circuit package includes a plurality of interconnects. A first logic circuitry of a first integrated circuit may produce a first signal that may be transmitted to a second integrated circuit. The integrated circuit package further includes interconnect circuitry disposed between the first and second integrated circuits. Multiplexing circuitry may select the first signal from second logic circuitry when the first logic circuitry is defective and may direct the signal as output signal to the second integrated circuit through a given interconnect.Type: GrantFiled: October 19, 2012Date of Patent: July 22, 2014Assignee: Altera CorporationInventors: Siang Poh Loh, Chooi Pei Lim, Yee Liang Tan, Kar Keng Chua
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Patent number: 8786080Abstract: Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.Type: GrantFiled: March 11, 2011Date of Patent: July 22, 2014Assignee: Altera CorporationInventors: Chooi Pei Lim, Jordan Plofsky, Yee Liang Tan, Teik Tiong Toong
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Patent number: 8758961Abstract: A mask set is described. In one implementation, the mask set includes: a first layer mask including a plurality of first tiles of a first tile size; and a second layer mask including a plurality of second tiles of a second tile size, where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described. In one implementation, the method includes: using a first layer mask having a first tile size to fabricate a first layer of a first IC of the plurality of ICs and a first layer of a second IC of the plurality of ICs; and using a second layer mask having a second tile size to fabricate a second layer of the first IC, where the second tile size is different from the first tile size.Type: GrantFiled: September 27, 2011Date of Patent: June 24, 2014Assignee: Altera CorporationInventors: Jordan Plofsky, Chooi Pei Lim, Danny Biran, Francis Man-Chit Chow
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Patent number: 8683405Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.Type: GrantFiled: March 13, 2012Date of Patent: March 25, 2014Assignee: Altera CorporationInventors: Keong Hong Oh, Yee Liang Tan, Siang Poh Lob, Chooi Pei Lim
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Publication number: 20140077839Abstract: Clock, distribution circuitry for a structured ASIC device includes a deterministic portion, and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served, from that predetermined, location.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicant: ALTERA CORPORATIONInventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
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Patent number: 8595658Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.Type: GrantFiled: June 26, 2008Date of Patent: November 26, 2013Assignee: Altera CorporationInventors: Chooi Pei Lim, Joo Ming Too, Yew Fatt Kok, Kar Keng Chua
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Publication number: 20120228760Abstract: Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Applicant: ALTERA CORPORATIONInventors: Chooi Pei Lim, Jordan Plofsky, Yee Liang Tan, Teik Tiong Toong
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Publication number: 20120169362Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Inventors: Keong Hong Oh, Yee Liang Tan, Siang Poh Lob, Chooi Pei Lim