Patents by Inventor Choon Heung Lee

Choon Heung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10388643
    Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 20, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Young Kim, Doo Hyun Park, Ju Hoon Yoon, Seong Min Seo, Glenn Rinne, Choon Heung Lee
  • Patent number: 10177117
    Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: January 8, 2019
    Assignee: Amkor Technology Inc.
    Inventors: Won Bae Bang, Ju Hoon Yoon, Ji Young Chung, Byong Jin Kim, Gi Jeong Kim, Choon Heung Lee
  • Patent number: 10115705
    Abstract: A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: October 30, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jin Young Kim, No Sun Park, Yoon Joo Kim, Choon Heung Lee, Jin Han Kim, Seung Jae Lee, Se Woong Cha, Sung Kyu Kim, Glenn Rinne
  • Publication number: 20170323862
    Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Inventors: Boo Yang Jung, Jong Sik Paek, Choon Heung Lee, In Bae Park, Sang Won Kim, Sung Kyu Kim, Sang Gyu Lee
  • Publication number: 20170271315
    Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.
    Type: Application
    Filed: April 18, 2017
    Publication date: September 21, 2017
    Inventors: Jin Young Kim, Doo Hyun Park, Ju Hoon Yoon, Seong Min Seo, Glenn Rinne, Choon Heung Lee
  • Patent number: 9748154
    Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: August 29, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Boo Yang Jung, Jong Sik Paek, Choon Heung Lee, In Bae Park, Sang Won Kim, Sung Kyu Kim, Sang Gyu Lee
  • Patent number: 9627348
    Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: April 18, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Dong Su Ryu, Choon Heung Lee, Min Ho Kim, Choong Hoe Kim, Ju Hoon Yoon, Chan Ha Hwang, Yang Gyoo Jung
  • Patent number: 9627368
    Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 18, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Young Kim, Doo Hyun Park, Ju Hoon Yoon, Seong Min Seo, Glenn Rinne, Choon Heung Lee
  • Publication number: 20160343688
    Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.
    Type: Application
    Filed: April 19, 2016
    Publication date: November 24, 2016
    Applicant: Amkor Technology, Inc.
    Inventors: Won Bae Bang, Ju Hoon Yoon, Ji Young Chung, Byong Jin Kim, Gi Jeong Kim, Choon Heung Lee
  • Publication number: 20160322334
    Abstract: A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 3, 2016
    Inventors: Jin Young Kim, No Sun Park, Yoon Joo Kim, Choon Heung Lee, Jin Han Kim, Seung Jae Lee, Se Woong Cha, Sung Kyu Kim, Glenn Rinne
  • Patent number: 9412729
    Abstract: A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package comprising a mounting board. At least one second semiconductor die may be mounted on the mounting board, and one or more leads may be electrically connected to the mounting board and/or the second semiconductor die. An adhesion member may bond the first package to the second package, and an encapsulant may encapsulate the first package and the second package. the circuit board, the mounting board, and the one or more leads may be arranged to surround the first semiconductor die and the second semiconductor die, and the plurality of leads may be electrically connected to the circuit board and to a constant potential or ground, to reduce the effects of external electromagnetic interference upon the semiconductor package.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: August 9, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Ji Young Chung, Choon Heung Lee, Glenn Rinne, Byong Jin Kim
  • Patent number: 9406639
    Abstract: A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 2, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Young Kim, No Sun Park, Yoon Joo Kim, Choon Heung Lee, Jin Han Kim, Seung Jae Lee, Se Woong Cha, Sung Kyu Kim, Glenn Rinne
  • Publication number: 20160049381
    Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.
    Type: Application
    Filed: January 8, 2015
    Publication date: February 18, 2016
    Inventors: Dong Su Ryu, Choon Heung Lee, Min Ho Kim, Choong Hoe Kim, Ju Hoon Yoon, Chan Ha Hwang, Yang Gyoo Jung
  • Publication number: 20150303170
    Abstract: A singulated substrate for a semiconductor device may include a singulated unit substrate comprising circuit patterns on a top surface and a bottom surface of the singulated unit substrate. A semiconductor die may be bonded to the top surface of the singulated unit substrate. An encapsulation layer may encapsulate the semiconductor die and cover the top surface of the singulated unit substrate. The side surfaces of the singulated unit substrate between the top surface and bottom surface of the singulated unit substrate may be coplanar with side surfaces of the encapsulation layer. The semiconductor die may be electrically coupled to the singulated unit substrate utilizing solder bumps. Solder balls may be formed on the circuit patterns on the bottom surface of the singulated unit substrate. An underfill material may be formed between the semiconductor die and the top surface of the singulated unit substrate.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 22, 2015
    Applicant: Amkor Technology, Inc.
    Inventors: Keun Soo Kim, Byoung Jun Ahn, Choon Heung Lee, Jin Young Kim, Dae Byoung Kang, Roger St. Amand
  • Publication number: 20150221601
    Abstract: A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.
    Type: Application
    Filed: August 1, 2014
    Publication date: August 6, 2015
    Inventors: Jin Young Kim, Ji Young Chung, Doo Hyun Park, Choon Heung Lee
  • Publication number: 20150041975
    Abstract: A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package comprising a mounting board. At least one second semiconductor die may be mounted on the mounting board, and one or more leads may be electrically connected to the mounting board and/or the second semiconductor die. An adhesion member may bond the first package to the second package, and an encapsulant may encapsulate the first package and the second package. the circuit board, the mounting board, and the one or more leads may be arranged to surround the first semiconductor die and the second semiconductor die, and the plurality of leads may be electrically connected to the circuit board and to a constant potential or ground, to reduce the effects of external electromagnetic interference upon the semiconductor package.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 12, 2015
    Inventors: Ji Young Chung, Choon Heung Lee, Glenn Rinne, Byong Jin Kim
  • Patent number: 8802494
    Abstract: The method of fabricating a semiconductor device may include forming a semiconductor die on a substrate, forming an interposer including at least one integrated circuit connected to the semiconductor die on the substrate or on the semiconductor die, and performing encapsulation to surround the semiconductor die and the interposer.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: August 12, 2014
    Assignee: Amkor Technology Korea, Inc.
    Inventors: Choon Heung Lee, Ki Cheol Bae, Do Hyun Na
  • Publication number: 20140147970
    Abstract: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 29, 2014
    Applicant: Amkor Technology, Inc.
    Inventors: Jin Young Kim, Doo Hyun Park, Ju Hoon Yoon, Seong Min Seo, Glenn Rinne, Choon Heung Lee
  • Publication number: 20140042600
    Abstract: A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 13, 2014
    Inventors: Jin Young Kim, No Sun Park, Yoon Joo Kim, Choon Heung Lee, Jin Han Kim, Seung Jae Lee, Se Woong Cha, Sung Kyu Kim, Glenn Rinne
  • Publication number: 20130109135
    Abstract: The method of fabricating a semiconductor device may include forming a semiconductor die on a substrate, forming an interposer including at least one integrated circuit connected to the semiconductor die on the substrate or on the semiconductor die, and performing encapsulation to surround the semiconductor die and the interposer.
    Type: Application
    Filed: April 24, 2012
    Publication date: May 2, 2013
    Applicant: AMKOR TECHNOLOGY KOREA, INC.
    Inventors: Choon Heung LEE, Ki Cheol BAE, Do Hyun NA