Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

Abstract: According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.

Abstract: This technology provides an electronic device and method for fabricating the same. A method for fabricating an electronic device comprising a transistor includes forming a junction region which is partially amorphized in the semiconductor substrate at a side of the gate; forming a metal layer over the junction region; and performing a heat treatment process on the metal layer into a metal-semiconductor compound layer while crystallizing the junction region.

Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

Abstract: According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.

Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

Abstract: A variable resistance memory device includes a first electrode, a second electrode, a first variable resistance layer formed over the first electrode and including at least two kinds of metal oxides, and a second variable resistance layer interposed between the first variable resistance layer and the second electrode and including a metal oxide.

Abstract: A phase-change random access memory (PCRAM) device and a method of manufacturing the same. The PCRAM device includes memory cells that each include a semiconductor substrate having a switching element, a lower electrode formed on the switching element, a phase-change layer formed on the lower electrode, and an upper electrode formed on the phase-change layer; and a porous insulating layer arranged to insulate one memory cell from another memory cell of the memory cells.

Abstract: A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

Abstract: A method for fabricating a non-volatile memory device with a three-dimensional structure includes forming a pipe gate conductive layer on a substrate, forming a pipe channel hole in the pipe gate conductive layer, burying a first sacrificial layer in the pipe channel hole, stacking interlayer dielectric layers and gate conductive layers on the pipe gate conductive layer including the first sacrificial layer, forming a pair of cell channel holes in the interlayer dielectric layers and the gate conductive layers, forming a second sacrificial layer on a resultant structure including the pair of cell channel holes, and forming a third sacrificial layer with etching selectivity relative to the second sacrificial layer on the second sacrificial layer and filling the cell channel holes with the third sacrificial layer.

Abstract: A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

Abstract: The present invention relates to a method of forming an insulating film in a semiconductor device. After a mixed gas of alkyl silane gas and N2O gas is supplied into the deposition equipment, a radio frequency power including a short pulse wave for causing incomplete reaction upon a gas phase reaction is applied to generate nano particle. The nano particle is then reacted to oxygen radical to form the insulating film including a plurality of nano voids. A low-dielectric insulating film that can be applied to the nano technology even in the existing LECVD equipment is formed.

Abstract: The present invention relates to a method for forming an insulating layer in a semiconductor device. After a first oxide film is formed in a trench, an impurity remaining on the first oxide film in the process of etching the first oxide film using a gas containing fluorine is stripped using oxygen plasma or hydrogen plasma. Thus, it can prevent degradation of device properties due to diffusion of the impurity without additional equipment. Therefore, it can help improve reliability of a next-generation device.

Abstract: A method for forming an isolation film of a semiconductor device is disclosed which includes forming trenches in a semiconductor substrate, forming a first HDP oxide film in the formed trenches, performing an etch-back process using a mixing gas of C2F6 gas and O2 gas to form vertical walls in the first HDP oxide films and forming a second HDP oxide film on the resulting structure. The characteristics of a device can be improved because diffusion of F ions in a FSG film formed on the first HDP oxide film is minimized.

Abstract: The present invention is provided to a semiconductor device and a method of fabricating the same. A spacer consisting of SiCxHy or SiOCxHy having a low dielectric constant is formed at the sidewall of a trench or a hole that is formed in an interlayer insulating film. It is therefore possible to reduce the dielectric constant while reducing critical dimension loss of the trench or the hole. Therefore, the present invention has advantages that it can enhance the operating speed of the device by minimizing parasitic capacitance and prohibiting RC delay and crosstalk.

Abstract: The present invention is provided to a semiconductor device and a method of fabricating the same. A spacer consisting of SiCxHy or SiOCxHy having a low dielectric constant is formed at the sidewall of a trench or a hole that is formed in an interlayer insulating film. It is therefore possible to reduce the dielectric constant while reducing critical dimension loss of the trench or the hole. Therefore, the present invention has advantages that it can enhance the operating speed of the device by minimizing parasitic capacitance and prohibiting RC delay and crosstalk.

Abstract: A method of forming a copper wiring in a semiconductor device. The method can prevent an increase of a dielectric constant of a low dielectric constant film and making bad deposition of a copper anti-diffusion film, due to infiltration of an organic solvent, an etch gas, etc. into the low dielectric constant film exposed at the side of a damascene pattern during a wet cleaning process for removing polymer generating when a portion of the low dielectric constant film is etched to form the damascene pattern or during a photoresist pattern strip process. In order accomplish these purpose, a CFXHY polymer layer is changed to a SiCH film using SiH4 plasma without removing the polymer layer formed at the side of the damascene pattern. Therefore, infiltration of an organic solvent or an etch gas can be prevented due to the SiCH film having a condensed film quality and a good mechanical strength.

Abstract: The present invention relates to a method of forming an insulating film in a semiconductor device. After a mixed gas of alkyl silane gas and N2O gas is supplied into the deposition equipment, a radio frequency power including a short pulse wave for causing incomplete reaction upon a gas phase reaction is applied to generate nano particle. The nano particle is then reacted to oxygen radical to form the insulating film including a plurality of nano voids. A low-dielectric insulating film that can be applied to the nano technology even in the existing LECVD equipment is formed.

Abstract: A method of forming a copper wiring in a semiconductor device. The method can prevent an increase of a dielectric constant of a low dielectric film and making bad deposition of a copper anti-diffusion film, due to infiltration of an organic solvent, an etch gas, etc. into the low dielectric film exposed at the side of a damascene pattern during a wet cleaning process for removing polymer generating when a portion of the low dielectric film is etched to form the damascene pattern or during a photoresist pattern strip process. In order accomplish these purpose, a polymer layer is changed to a SiCH film using SiH4 plasma without removing the polymer layer formed at the side of the damascene pattern. Therefore, infiltration of an organic solvent or an etch gas can be prevented due to the SiCH film having a condense film quality and a good mechanical strength. Also, the SiCH film serves as a copper anti-diffusion film and in structure, supports a porous low dielectric film having a weak mechanical strength.