Patents by Inventor Choon Kun Ryu

Choon Kun Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6190233
    Abstract: A method and an apparatus for depositing a dielectric layer to fill in a gap between adjacent metal lines. In preferred embodiments of the method, a first dielectric layer is deposited over the lines and subsequently etched using both chemical and physical etchback steps. After the etchback steps are completed, a second dielectric layer is deposited over the first dielectric layer to fill in the gap.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: February 20, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Soonil Hong, Choon Kun Ryu, Michael P. Nault, Kaushal K. Singh, Anthony Lam, Virendra V. S. Rana, Andrew Conners
  • Patent number: 5990000
    Abstract: A method and an apparatus for depositing a dielectric layer to fill in a gap between adjacent metal lines. In preferred embodiments of the method, a first dielectric layer is deposited over the lines and subsequently etched using both chemical and physical etchback steps. After the etchback steps are completed, a second dielectric layer is deposited over the first dielectric layer to fill in the gap.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: November 23, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Soonil Hong, Choon Kun Ryu, Michael P. Nault, Kaushal K. Singh, Anthony Lam, Virendra V. S. Rana, Andrew Conners
  • Patent number: 5908672
    Abstract: A planarized passivation layer is described. A planarized passivation layer of the present invention preferably includes a fluorosilicate glass (FSG) layer and a silicon nitride layer. The FSG layer is preferably deposited using triethoxyfluorosilane (TEFS) and tetraethoxyorthosilicate (TEOS). The inclusion of fluorine in the process chemistry provides good gap-fill characteristics in the film thus formed. The TEFS-based process employed by the present invention employs a low deposition rate, on the order of less than about 4500 .ANG./min, and preferably above 3000 .ANG./min, when depositing the FSG layer. The use of low deposition rate results in a positively sloped profile, preventing the formation of voids during the deposition of the FSG layer and the silicon nitride layer.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: June 1, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Choon Kun Ryu, Judy H. Huang, David Cheung