Abstract: A display device includes: a display including a plurality of pixels; and a controller configured to: receive an external input image signal, adjust the external input image signal to compensate for brightness deviations of the pixels, and transmit corresponding image data signals to the pixels, wherein the controller includes: a data input section configured to receive the external input image signal and transmit a test image data signal to the pixels through a data driver, a luminance information extracting section configured to: extract brightness information for the pixels after displaying a test image in accordance with the test image data signal, and calculate first, second, and third parameters, using the brightness information, and a data compensating section configured to generate the image data signals by adjusting the external input image signal based on the first, second, and third parameters.

Abstract: A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2^K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

Abstract: A pixel luminance compensating unit is disclosed. In one aspect, the disclosed pixel luminance compensating unit includes an uncompensated gray-level region processing unit configured to generate first output-data by processing first input-data corresponding to a first portion of an input luminance curve corresponding to an uncompensated gray-level region. The disclosed unit further includes a compensated gray-level region processing unit configured to generate second output-data by processing second input-data corresponding to a second portion of the input luminance curve corresponding to a compensated gray-level region.

Abstract: A temperature sensing device includes a first frequency generator for generating a first clock signal having a first frequency that is constant regardless of a temperature; a second frequency generator for generating a second clock signal having a second frequency that is changed according to the temperature; and a data holding unit for outputting a temperature code indicating a number of pulses of the second clock signal counted for a reference time at which a number of pulses of the first clock signal reaches a predetermined threshold. The temperature sensing device does not require a reference clock signal input from the outside and is insensitive to the change in the process, thereby being capable of improving the performance of the temperature sensing device.

Abstract: A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.

Abstract: A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2?K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

Abstract: A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially formed on the active region, and source/drain regions separated across the gate stack, but the gate insulation layer of the fuse/anti-fuse transistor is selectively damaged during fabrication.

Abstract: A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.

Abstract: A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially formed on the active region, and source/drain regions separated across the gate stack, but the gate insulation layer of the fuse/anti-fuse transistor is selectively damaged during fabrication.

Abstract: A high voltage generating circuit and semiconductor memory device having the same are provided, where the high voltage generating circuit includes a pumping driving signal generating means for sequentially generating n-number of pumping driving signals in response to m-number of control signals, where n is greater than m; n-number of pumping control signal generating circuits for generating n-number of pumping control signals in response to the n-number of pumping driving signals, respectively; and n-number of pumping circuits for performing a pumping operation to pump a high voltage level in response to each of the n-number pumping control signals; such that it is possible to reduce a row cycle time regardless of a pumping cycle time, thereby achieving a high speed operation.

Abstract: An apparatus for generating a column select line signal in a semiconductor memory device includes a column select line signal generator configured to generate a column select line signal in response to a column select line enable signal. The column select line signal has a first pulse width when the column select line signal generator is in a first operational mode and a second pulse width when the column select line signal generator is in a second operational mode. The second pulse width is longer than the first pulse width.

Abstract: An apparatus for generating a column select line signal in a semiconductor memory device includes a column select line signal generator configured to generate a column select line signal in response to a column select line enable signal. The column select line signal has a first pulse width when the column select line signal generator is in a first operational mode and a second pulse width when the column select line signal generator is in a second operational mode. The second pulse width is longer than the first pulse width.

Abstract: A high voltage generating circuit and semiconductor memory device having the same are provided, where the high voltage generating circuit includes a pumping driving signal generating means for sequentially generating n-number of pumping driving signals in response to m-number of control signals, where n is greater than m; n-number of pumping control signal generating circuits for generating n-number of pumping control signals in response to the n-number of pumping driving signals, respectively; and n-number of pumping circuits for performing a pumping operation to pump a high voltage level in response to each of the n-number pumping control signals; such that it is possible to reduce a row cycle time regardless of a pumping cycle time, thereby achieving a high speed operation.

Abstract: Provided are a circuit and a method for transforming a data input/output format of a semiconductor memory device which is capable of generating various types of data patterns when the number of memory cells connected to one column selection line is greater than the number of data input pins. The circuit for transforming a data input/output format of a semiconductor memory device includes a first transmission circuit, a second transmission circuit, and a mode register set (MRS). The first transmission circuit is activated when a first test mode signal is enabled, receives n data inputs from n data input ends, and transmits the n data inputs to m memory cells. Here, n and m are natural numbers and m is greater than n. The second transmission circuit is activated when a second test mode signal is enabled, receives n data inputs from the n data input ends, and transmits the n data inputs to the m memory cells.

Abstract: A method for controlling column decoder enable timing including determining if there is a gap between a data write command and a data read command which occur consecutively; generating a timing control signal for delaying received clock signal for an amount of time which depends on the determination result; and activating a column decoder in response to the timing control signal. Generating a timing control signal includes generating a timing control signal having a first delay time if there is a gap and generating a timing control signal having a second delay time if there is no gap, when the first delay time is shorter than the second delay time. An effect is an increase in the maximum operating frequency of a system for outputting data.

Abstract: Provided are a circuit and a method for transforming a data input/output format of a semiconductor memory device which is capable of generating various types of data patterns when the number of memory cells connected to one column selection line is greater than the number of data input pins. The circuit for transforming a data input/output format of a semiconductor memory device includes a first transmission circuit, a second transmission circuit, and a mode register set (MRS). The first transmission circuit is activated when a first test mode signal is enabled, receives n data inputs from n data input ends, and transmits the n data inputs to m memory cells. Here, n and m are natural numbers and m is greater than n. The second transmission circuit is activated when a second test mode signal is enabled, receives n data inputs from the n data input ends, and transmits the n data inputs to the m memory cells.

Abstract: A method for controlling column decoder enable timing including determining if there is a gap between a data write command and a data read command which occur consecutively; generating a timing control signal for delaying received clock signal for an amount of time which depends on the determination result; and activating a column decoder in response to the timing control signal. Generating a timing control signal includes generating a timing control signal having a first delay time if there is a gap and generating a timing control signal having a second delay time if there is no gap, when the first delay time is shorter than the second delay time. An effect is an increase in the maximum operating frequency of a system for outputting data.

Abstract: A synchronous DRAM (SDRAM) having a posted column access strobe (CAS) latency and a method of controlling CAS latency are provided. In order to control a delay time from the application of a CAS command and a column address to the beginning of memory, reading or writing operations in units of clock cycles, a first method of programing the delay time as a mode register set (MRS) and a second method of detecting the delay time using an internal signal and an external signal, are provided. In the second method, the SDRAM can include a counter for controlling the CAS latency. This counter controls the CAS latency of the SDRAM by generating a signal for controlling the CAS latency according to the number of clock cycles of a clock signal from the generation of a row access command to a column access command in the same memory bank and reading the signal.

Abstract: A novel parallel bit test circuit is provided to test a semiconductor memory device which comprises a number of memory cell arrays each having a plurality of memory cells, a word line provided in each memory cell array to commonly connect with the plurality of memory cells, and a plurality of I/O (input/output) lines respectively connected with the plurality of memory cells of each memory cell array. The parallel bit test circuit for testing the plurality of memory cells in parallel bits comprises a comparator for comparing the data of the memory cells with an externally input data to produce a test signal applied to a data I/O terminal.

Abstract: A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and controlling an isolation gate. The refresh row active signal is activated for a constant period. A plurality of block select signals are selectively activated when the refresh row active signal is active. The latch isolation control signal is set according to a block select signal and reset by an adjacent block select signal related to the other isolation gate connected to the same bit line sense amplifier of the block. In the step of controlling the isolation gate, when the latch isolation control signal is active, the isolation gates are turned on, and the other isolation gates connected to the same bit line sense amplifier are turned off.