Abstract: A defective cell repairing circuit for repairing a defective cell in a packaged semiconductor memory device enables repair mode operations for mapping an address of a detected defective cell to a redundant cell. The address of the defective cell is programmed by selectively cutting fuses corresponding to each bit of the defective cell address. The defective cell address programming operation uses input terminals on the packaged semiconductor memory device which are used for address signals in a normal operation mode, so that no additional pins are required. Repair mode operations are prevented after the repair mode is completed. Thereafter, an external address supplied to the semiconductor memory device is compared with the programmed defective cell address determined by the state of the fuses, and a redundant cell is selected if the two addresses correspond.

Abstract: A semiconductor memory device with redundancy structure having a normal memory cell array having a plurality of normal memory cells arranged in row and column directions and a redundant memory cell array having a plurality of redundant memory cells, includes a redundant column selecting circuit for comparing an externally applied column address signal and a programmed defective column address signal to generate a redundant column selection signal. The redundant column selecting circuit has a programming circuit portion for producing the programmed defective column address signal by programming a defective column address corresponding to a defective column.

Abstract: The present invention relates to a semiconductor memory device and more particularly to a multi-bit test circuit which is capable of testing a data access operation of a plurality of memory cells at the same time.