Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

Abstract: A light-emitting device is applicable to a backlight module. The light-emitting device includes a substrate, a light-emitting diode (LED) and an encapsulation body. The encapsulation body is on the substrate and covers the LED. The encapsulation body includes a base and a lens. The base has a base surface. The lens has a lens surface. The lens surface conforms to a cubic Bezier curve. The cubic Bezier curve has a start point and an end point. The start point of the cubic Bezier curve is at the base surface. The end point of the cubic Bezier curve corresponds to the center of the LED. The lens surface is provided with a concave portion at the end point. The lens increases the light-emitting angle of the LED, so that the spacing between light-emitting devices can be increased, thereby reducing the number of light-emitting devices to be used and the costs.

Abstract: A projection device, a projection system and a method for calibrating projected image are provided. The projection device and an external projection device the same image source and respectively project an image and another image corresponding to the image source. The same portion of the image source where the two images overlap each other forms an overlapping area. The projection device includes a lens, a light shielding member and a processor. The light shielding member is disposed on the lens. The processor controls the light shielding member to selectively shade a partial area of the lens according to the brightness of the image source, wherein the partial area corresponds to the overlapping area.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: An imaging lens assembly includes a first optical element and a low-reflection layer. The first optical element has a central opening, and includes a first surface, a second surface and a first outer diameter surface. The first outer diameter surface is connected to the first surface and the second surface. The low-reflection layer is located on at least one of the first surface and the second surface, and includes a carbon black layer, a nano-microstructure and a coating layer. The nano-microstructure is directly contacted with and connected to the carbon black layer, and the nano-microstructure is farther from the first optical element than the carbon black layer from the first optical element. The coating layer is directly contacted with and connected to the nano-microstructure, and the coating layer is farther from the first optical element than the nano-microstructure from the first optical element.

Abstract: A lens assembly module includes a base, a cover, a lens unit, an elastic element, at least two conductive elements, at least one AF coil element and at least two first magnetic elements. The cover is coupled to the base. The lens unit is movably disposed in the cover. The elastic element is coupled to the lens unit. The conductive elements are coupled to the lens unit. The AF coil element is disposed on the lens unit, and two ends of the AF coil element are electrically connected to the conductive elements, respectively. The first magnetic elements are disposed in the cover. A part of each of the inner portions is overlapped along a direction parallel to an optical axis and electrically connected to each conductive element. The AF coil element and the conductive elements are electrically connected by a welding method.

Abstract: The present disclosure provides GLP-1R agonists, and compositions, methods, and kits thereof. Such compounds are generally useful for treating a GLP-1R mediated disease or condition in a human.

Abstract: A semiconductor tester and a method for calibrating a probe card and a device under testing (DUT) are disclosed. The semiconductor tester includes: a support platform, including a support surface and configured to be able to move along a direction parallel to the support surface and rotate around a rotating shaft perpendicular to the support surface; a probe card including a plurality of probes stretching towards the support platform; and an alignment assembly, including: at least two first laser emitting apparatuses emitting a plurality of first laser beams; and a second laser emitting apparatus emitting a plurality of second laser beams. The first laser beams and the second laser beams are perpendicular to each other and are each arranged sequentially along a direction perpendicular to the support surface. The semiconductor tester aligns a probe card to a DUT with improved accuracy, thereby preventing the damage to the probe card.

Abstract: The disclosure is directed to a timing controller having a mechanism for frame synchronization, a display panel having the timing controller thereof, and a display system having the timing controller thereof. According to an aspect of the disclosure, the disclosure provides an integrated circuit which includes a timing controller to transmit a first TE signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal.

Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: An electronic device is provided. The electronic device includes a display, a substrate, and an anti-explosion layer. The substrate is disposed on the display. The anti-explosion layer is disposed between the substrate and the display, and the anti-explosion layer has a tensile strength in a range from 10 MPa to 30 MPa.

Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Abstract: A camera module includes a metal yoke, a holding base, a plastic barrel, a plurality of plastic lens elements, a leaf spring pair and a coil element. The holding base is connected to the metal yoke and defines an inner space. The holding base has a through hole which is corresponding to an opening of the metal yoke. The plastic barrel is movably disposed in the inner space. The plastic lens elements are disposed in the plastic barrel. The leaf spring pair includes two leaf springs which are located on a same plane and connected to the plastic barrel. The coil element surrounds an outer surface of the plastic barrel and electrically connected to the leaf spring pair, wherein two ends of the coil element is connected to the leaf springs by a thermal pressing method.

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

Abstract: A plastic lens element includes an optical effective portion and a peripheral portion. The peripheral portion surrounds the optical effective portion and includes a peripheral surface and an optical inspecting structure. The optical inspecting structure is disposed between the optical effective portion and the peripheral surface and includes a first optical inspecting surface and a second optical inspecting surface. The first optical inspecting surface and the second optical inspecting surface are disposed on two sides of the peripheral portion respectively and correspond to each other.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A method for Radio Access Network (RAN) Notification Area (RNA) management for a user equipment (UE) is provided. The method receives a first Radio Resource Control (RRC) message having a first Radio Access Network (RAN) Notification Area (RNA) configuration. The method then stores the first RNA configuration, when the UE is in one of an RRC Connected state, an RRC Inactive state, or transitioning between the RRC Inactive state and the RRC Connected state. The method applies an RNA update procedure based on the first RNA configuration when the UE is in the RRC Inactive state.