Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030340
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Inventors: YI-HUAN CHEN, CHIEN-CHIH CHOU, SZU-HSIEN LIU, KONG-BENG THEI
  • Publication number: 20240032439
    Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20240030256
    Abstract: A semiconductor image sensing structure includes a semiconductor substrate having a front side and a back side, a pixel sensor disposed in the semiconductor substrate, a transistor disposed over the front side of the semiconductor substrate, and a reflective structure disposed over the front side of the semiconductor substrate. A gate structure of the transistor and the reflective structure include a same material. A top surface of the gate structure of the transistor and a top surface of the reflective structure are aligned with each other.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: WEI-LIN CHEN, YU-CHENG TSAI, CHUN-HAO CHOU, KUO-CHENG LEE
  • Publication number: 20240028810
    Abstract: Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng, Yung-Hsu Chuang
  • Publication number: 20240027430
    Abstract: The disclosure provides a method for identifying a bio-entity including a cell type and count in a sample. The method includes: providing a device comprising a first plate, a second plate, and a patterned structural element; depositing the sample between the first and second plates; reducing the spacing of the first and second plates so that the first and second plates are in a closed configuration to compress the sample into a layer; and imaging the sample to obtain an image; and measuring and analyzing the image against a database generated with a machine learning model to obtain the bio-entity of the sample. The sample can be a blood sample, and the method can be a white blood cell differential test conducted with a mobile phone.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 25, 2024
    Applicant: Essenlix Corporation
    Inventors: Stephen Y. CHOU, Yu SUN, Wei DING, Ji Qi, Mingquan WU, Shengjian CAI, Wu CHOU
  • Publication number: 20240027504
    Abstract: The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is ? times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 25, 2024
    Inventors: MAO-HSUAN CHOU, RUEY-BIN SHEEN, CHIH-HSIEN CHANG
  • Publication number: 20240027880
    Abstract: An imaging lens assembly module has an optical axis, and includes a lens barrel and an optical element set. The lens barrel includes an object-side portion, a tubular portion and a tip-end minimal aperture. The object-side portion includes a first assembling surface. The tubular portion includes a plurality of second assembling surfaces. The optical element set includes at least one light blocking sheet and at least one optical lens element. The light blocking sheet includes an object-side surface, an image-side surface and an inner opening surface. The optical lens element includes an optical effective portion and a peripheral portion. The object-side portion of the lens barrel includes a first reversing inclined surface gradually enlarged from the tip-end minimal aperture to the image side of the lens barrel, and the first reversing inclined surface is not contacted with the optical element set.
    Type: Application
    Filed: October 3, 2023
    Publication date: January 25, 2024
    Inventors: Kuan-Ming CHEN, Hsiang-Chi TANG, Lin-An CHANG, Cheng-Chen LIN, Ming-Ta CHOU
  • Publication number: 20240024407
    Abstract: The present invention provides a pharmaceutical composition comprising a binary conjugate, DC009, which is a conjugate of a thrombolytic peptide (Pro-Ala-Lys) and a tetrahydroisoquinoline compound having two C1-4 alkyl groups via a lysine linking arm, and a pharmaceutical acceptable carrier. The composition has a pH less than 6.5, preferably has a pH about pH 2-5.5 The composition may comprise a pharmaceutical acceptable excipient such as mannitol, sorbitol, sucrose, lactose, or trehalose.
    Type: Application
    Filed: June 12, 2023
    Publication date: January 25, 2024
    Inventor: David Chih-Kuang Chou
  • Publication number: 20240030318
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first plurality of vertically aligned semiconductor layers disposed over a substrate and a first gate electrode layer surrounding each of the first plurality of vertically aligned semiconductor layers. The first gate electrode layer includes first one or more work function metal layers disposed between adjacent semiconductor layers of the first plurality of vertically aligned semiconductor layers and two first conductive layers disposed on opposite sides of the first one or more work function metal layers. The first conductive layers include a material different from the first one or more work function metal layers. The first gate electrode layer further includes a second conductive layer disposed on the first conductive layers, and the second conductive layer and the first conductive layers include a same material.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Chi-Yu CHOU, Yueh-Ching PAI
  • Publication number: 20240025723
    Abstract: A dual-mode fluid connector includes: a hollow connecting element, comprising a chamber inside the hollow connecting element, wherein a protuberant block element is arranged on an inner surface of the chamber; a material tube, positioned on the hollow connecting element and connected through the chamber; a cleaning tube, positioned on the hollow connecting element and connected through the chamber; a head portion, positioned on one terminal of the hollow connecting element and having a connecting opening, wherein the connecting opening can be detachably connected to a material container; a rear portion, positioned on another terminal of the hollow connecting element and having a through hole; and a rod, inserted into the chamber via the through hole; and a rotatable element, covered on the rear portion and engaged with the rod and comprising a guiding element.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Applicant: Botrista Technology, Inc.
    Inventors: Yu-Min LEE, Wu-Chou KUO
  • Publication number: 20240026362
    Abstract: Provided are interfering RNAs (e.g., siRNAs) targeting SARS-CoV (e.g., the POL, Spike, Helicase, or Envelop gene thereof) and therapeutic uses thereof for inhibiting SARS-CoV infection and/or treating diseases associated with the infection (e.g., COVID-19).
    Type: Application
    Filed: December 3, 2021
    Publication date: January 25, 2024
    Applicants: MICROBIO (SHANGHAI) CO. LTD., ONENESS BIOTECH CO. LTD.
    Inventors: Yi-Chung CHANG, Chi-Fan YANG, Yi-Fen CHEN, Chia-Chun YANG, Yuan-Lin CHOU
  • Publication number: 20240023807
    Abstract: An optical biometer including a light source, a first-stage coupler, a first and a second second-stage coupler, a first and a second optical path difference generator, a first and a second optical component set, a first and a second detection device is disclosed. The first-stage coupler receives an incident light from the light source and emits first and second first-stage lights. The first second-stage coupler receives the first first-stage light and emits first and second second-stage lights. The second second-stage coupler receives the second first-stage light and emits third and fourth second-stage lights. The first/second optical path difference generator generates the first/fourth second-stage light with the first/second optical path difference. The first/second optical component set emits the second/third second-stage light to a first/second position of an eye and receives a first/second reflected light. The first/second detector receives a first/second detection light.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 25, 2024
    Inventors: Che-Liang TSAI, William WANG, Chung-Ping CHUANG, Sung-Yang WEI, Hsuan-Hao CHAO, Chung-Cheng CHOU
  • Publication number: 20240027811
    Abstract: A display device, including a first display panel, a second display panel, and a first optical structure layer, is provided. The first display panel has a first display surface emitting light toward a first direction. The second display panel has a second display surface emitting light toward a second direction, wherein the first direction is different from the second direction. The first optical structure layer is disposed on the first display panel, wherein a glossiness of the first optical structure layer is between 4 GU and 35 GU, and a reflectivity of specular component included (SCI) of the first optical structure layer is between 3% and 6%. The display device provided by the disclosure can reduce the influence of ambient light from the outside on a displayed image.
    Type: Application
    Filed: June 8, 2023
    Publication date: January 25, 2024
    Applicant: Innolux Corporation
    Inventors: Yu-Chun Hsu, Wei-Ming Chu, Yi-Hui Lee, Yung-Chih Cheng, Kuan-Chou Chen, Sheng-Nan Fan
  • Publication number: 20240028342
    Abstract: An information handling system includes multiple dual in-line memory modules (DIMMs) and a basic input/output system (BIOS). The DIMMs form a memory system of the information handling system. The BIOS begins a system boot of the information handling system, and performs a first memory reference code training. Based on the first memory reference code training, the BIOS discovers a bad DIMM of the DIMMs, and stores information associated with the bad DIMM. The BIOS reboots the information handling system. During the reboot, the BIOS retrieves the information associated with the bad DIMM. The BIOS disables a slot associated with the bad DIMM. In response to the slot being disabled, the BIOS performs a second memory reference code training. Based on the second memory reference code training, the BIOS downgrades the memory system to a closest possible DIMM population.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: Ching-Lung Chao, Hsin-Chieh Wang, Wei G. Liu, Yu-Hsuan Chou
  • Publication number: 20240025721
    Abstract: A dual-mode fluid connector includes: a hollow connecting element, comprising a chamber inside the hollow connecting element; a material tube, positioned on the hollow connecting element and connected through the chamber; a cleaning tube, positioned on the hollow connecting element and connected through the chamber; a head portion, positioned on one terminal of the hollow connecting element and having a connecting opening, wherein the connecting opening can be detachably connected to a material container; a rear portion, positioned on another terminal of the hollow connecting element and having a through hole; a rod, inserted into the chamber via the through hole; and a rotatable element, covered on the rear portion and comprising a block portion, wherein the block portion is positioned in an interior of the rotatable element and arranged to operably engage with the outer flange.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Applicant: Botrista Technology, Inc.
    Inventors: Yu-Min LEE, Wu-Chou KUO
  • Patent number: 11881616
    Abstract: A smart ring includes an antenna chip and a metal ring used as an antenna, and the antenna chip is electrically connected to the metal ring to form an antenna circuit. The metal body of the smart ring is designed as a composition structure of the antenna circuit, that is, the antenna is integrated into the metal ring, the space for accommodating the antennas and the cost for additional physical antennas are saved, and the design flexibility and the competitiveness of the product are improved. Nickel-zinc ferrite is unnecessary, which can reduce the cost. The ring can keep the radiation characteristic of the circular antenna that is not susceptible to the interference from human body. The metal body of the ring is a metal structure, which can fulfill both of strength requirement and texture requirement of the structure, and at the same time has good antenna characteristics.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: January 23, 2024
    Assignees: INVENTEC APPLIANCES (PUDONG) CORPORATION, INVENTEC APPLIANCES CORP., INVENTEC APPLIANCES (SHANGHAI) CO. LTD.
    Inventors: Chun-Chieh Hsu, Chih-Hsuan Hsiao, Kuang-Chung Chou
  • Patent number: 11881527
    Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.
    Type: Grant
    Filed: September 12, 2021
    Date of Patent: January 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ling-Chun Chou, Yu-Hung Chang, Kun-Hsien Lee
  • Patent number: 11880747
    Abstract: An image recognition method, a training system for an object recognition model and a training method for an object recognition model are provided. The image recognition method includes the following steps. At least one original sample image of an object in a field and an object range information and an object type information in the original sample image are obtained. At least one physical parameter is adjusted to generate plural simulated sample images of the object. The object range information and the object type information of the object in each of the simulated sample images are automatically marked. A machine learning procedure is performed to train an object recognition model. An image recognition procedure is performed on an input image.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 23, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Cheng Lin, Sen-Yih Chou
  • Patent number: 11881392
    Abstract: A lamp and epitaxial processing apparatus are described herein. In one example, the lamp includes a bulb, a filament, and a plurality of filament supports disposed in spaced-apart relation to the filament, each of the filament supports having a hook support and a hook. The hook includes a connector configured to fasten the hook to the hook support, a first vertical portion extending from the connector toward the filament, and a rounded portion extending from an end of the first vertical portion distal from the connector and configured to wrap around the filament. A second vertical portion extends from an end of the rounded portion distal from the first vertical portion and the second vertical portion has a length between 60% and 100% of the length of the first vertical portion.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: January 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yao-Hung Yang, Shantanu Rajiv Gadgil, Kaushik Rao, Vincent Joseph Kirchhoff, Sagir Kadiwala, Munirah Mahyudin, Daniel Chou
  • Patent number: 11882121
    Abstract: The present invention provides a method for packet processing according to a access control list table, comprising: receiving a packet, wherein the packet includes a packet information and match items for matching; providing an access control list (ACL) codeword table; providing a mask table, wherein the ACL codeword table corresponds to the mask table; obtaining a hash key by performing a multiplexing logic operation, wherein the hash key is made by combining a multiplex result of the packet information and the mask table; obtaining a hash value by performing a hash function based on the hash key, wherein the hash value is composed of X+Y, wherein X is a signature table (hash table) index and Y is a key digest; performing a hash table indexing, based on the signature table index, wherein the signature table index is the index to an address of signature table; performing a fast pattern match, wherein the signature table contains signature fields, and if any second signature field in the signature table is mat
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: January 23, 2024
    Assignee: OPTICORE TECHNOLOGIES, INC.
    Inventors: Yi-Lung Hsiao, Chih-Liang Chou