Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10975889
    Abstract: A fan module and an electronic device are provided. The fan module includes a hub and a plurality of blades. The blades are mounted around the hub, and each of the blades has a first end that is connected to a periphery of the hub and a second end that is relatively away from the hub. A first axial direction distance in the axial direction is provided between a first point of the first end that is relatively away from the top surface and the top surface. A second axial direction distance in the axial direction is provided between a second point of the first end that is near the top surface and the top surface. A ratio of the second axial direction distance to the first axial direction distance is 0.4 to 0.5.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 13, 2021
    Assignee: Coretronic Corporation
    Inventors: Shih-Hang Lin, Chih-Cheng Chou
  • Patent number: 10978118
    Abstract: Disclosed is a DDR SDRAM signal calibration device capable to adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal pad configured to output a DQS signal; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and the DQS signal; and a calibration circuit configured to output a calibration signal according to the DQS enablement setting signal and at least one of the DQS enablement signal and the DQS signal so that the enablement signal setting circuit can maintain or adjust the DQS enablement setting according to the calibration signal.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 13, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Chi Yu, Fu-Chin Tsai, Chih-Wei Chang, Gerchih Chou
  • Patent number: 10978329
    Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Chih-Wei Huang, Kuo-Sheng Chuang, Cheng-Chung Chien
  • Patent number: 10977171
    Abstract: A method for creating a multi-namespace includes steps of: returning information of a namespace data structure according to a query command from, wherein the information of the namespace data structure comprises a maximum number and a total capacity of supportable namespace; receiving and determining whether a create command for creating a plurality of namespaces is correct, wherein the create command comprises a number of a namespace and a capacity of the namespace; and if the determination is correct, creating a global host logical-flash physical address (H2F) mapping table according to the create command, wherein a number of the global H2F mapping tables is independent of the maximum number of the supportable namespaces and the number of namespace. A method for accessing data in a multi-namespace is also provided.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 13, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Sheng Chou
  • Patent number: 10978345
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
  • Patent number: 10978795
    Abstract: An antenna structure includes a housing, a feed portion, a ground portion, a first radiator, and a second radiator. The housing includes a first radiating portion and a second radiating portion. The first radiator and the second radiator are both positioned in the housing. When the feed portion feeds current, the current flows through the first radiating portion and is grounded through the ground portion to activate a first operating mode. When the feed portion feeds current, the current is further coupled to the first radiator through the first radiating portion, and the first radiator activates a second operating mode. When the second radiator feeds current, the second radiator activates a third operating mode. When the second radiator feeds current, the current is further coupled to the second radiating portion through the second radiator, and the second radiating portion activates a fourth operating mode.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 13, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chang-Je Chen, Shu-Wei Jhang, Tun-Yuan Tsou, Yi-Te Chou, Yung-Chin Chen, Chang-Ching Huang
  • Patent number: 10978814
    Abstract: A high frequency antenna device is applied to an operation frequency band within a range of 20-45 GHz. The high frequency antenna device includes a substrate, an antenna array and a processing chip both respectively disposed on two opposite sides of the substrate, and two connectors mounted on the substrate. The antenna array includes a plurality of antennas arranged in at least one row. Each antenna is a dual-polarized metal sheet configured to be selectively operated in a horizontal polarization and a vertical polarization. The operation frequency band has a central frequency corresponding to a wavelength. Central points of any two adjacent antennas have an interval within a range of 0.25-0.75 times of the wavelength. The processing chip is electrically coupled to the antennas and the two connectors. The two connectors electrically correspond to the horizontal polarization and the vertical polarization of each of the antennas.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 13, 2021
    Assignee: AUDEN TECHNO CORP.
    Inventor: Jui-Hung Chou
  • Patent number: 10975202
    Abstract: A poly(amide-imide) is provided. The poly(amide-imide) is represented by formula (1), wherein R is a C6 aryl group, a C7-C8 aralkyl group, a C2-C6 alkoxyalkyl group, or a C3-C18 alkyl group; and 0.02?X?0.5.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Shao-Yen Chang, Chun-Hung Lin
  • Patent number: 10975487
    Abstract: Provided are an electrolytic copper foil, and an electrode and a copper-clad laminate comprising the same. The electrolytic copper foil comprises a base copper layer having a drum side and a deposited side; wherein the electrolytic copper foil has a Charpy impact strength from 0.4 J/mm2 to 5.8 J/mm2.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: April 13, 2021
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Huei-Fang Huang, Yao-Sheng Lai, Jui-Chang Chou
  • Patent number: 10976489
    Abstract: An optical device includes a waveguide configured to guide light, a taper integrated with the waveguide on a substrate configured for optical coupling, and an attenuator to degrade unwanted optical signal from the taper. The attenuator extends along one side of the taper, and includes one of a conductive structure, a doped structure and a refractive structure.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Feng Wei Kuo
  • Patent number: 10978589
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 13, 2021
    Assignee: United Microelectronics Corp.
    Inventors: Ling-Chun Chou, Kun-Hsien Lee
  • Patent number: 10977740
    Abstract: Disclosed is a system and method to automatically identify property-related risks through the use of computer vision, sensors, and/or building information models (BIMs). The ability to automatically identify a variety of hazards helps mitigate the associated risks, and thus reduces the number of accidents or fatalities that would otherwise occur. In some embodiments, a “risk map” can be generated by mapping the identified risks for a given property.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 13, 2021
    Assignee: AMERICAN INTERNATIONAL GROUP, INC.
    Inventors: Siddhartha Dalal, Devasis Bassu, Promiti Dutta, Ashwath Aithal, Liangkai Zhang, Alvin Chou, Michael P. Castelli
  • Publication number: 20210103655
    Abstract: A security monitoring apparatus and method for a vehicle network are provided. The apparatus transmits an indicator and an encryption key to a plurality of electronic control units via the controller area network interface. The apparatus receives a response code from each electronic control unit via the controller area network interface, wherein each of the response codes is generated by a serial number of each electronic control unit and the encryption key via a hash algorithm. The apparatus compares the response code returned by each electronic control unit according to a list, the encryption key and the hash algorithm to determine whether each electronic control unit correctly returns the response code. The apparatus determines to generate an alert signal when one of the electronic control units does not correctly return the response code.
    Type: Application
    Filed: November 25, 2019
    Publication date: April 8, 2021
    Inventors: I-Chou HUNG, Chih-Min SHIH, Hsing-Yu CHEN, Wen-Kai LIU
  • Publication number: 20210105722
    Abstract: A method performed by a User Equipment (UE) for power saving operations includes the UE receiving a first Radio Resource Control (RRC) configuration indicating at least one dormancy cell group, receiving a second RRC configuration indicating a first Bandwidth Part (BWP), on which the UE is configured with a dormant operation, for a serving cell, receiving a third RRC configuration indicating a second BWP, on which the UE is not configured with the dormant operation, for the serving cell, receiving a Power Saving Signal (PSS) including a bitmap, determining an active BWP of the serving cell as the first BWP after determining that a bit associated with the dormancy cell group in the bitmap is set to a first value, and determining the active BWP of the serving cell as the second BWP after determining that the bit is set to a second value.
    Type: Application
    Filed: September 25, 2020
    Publication date: April 8, 2021
    Inventors: HSIN-HSI TSAI, CHIA-HUNG WEI, YU-HSIN CHENG, WAN-CHEN LIN, CHIE-MING CHOU
  • Publication number: 20210103540
    Abstract: A network input/output structure of an electronic device includes a FPGA module, a multiple of UART voltage conversion transceivers, at least one network connector and at least one detection module. Each UART voltage conversion transceiver has an input/output pin definition of a brand specification of a network device. The FPGA module uses the detection module to detect the pin definition of an external network device to confirm the brand specification of the network device and turn on a voltage conversion chip of the UART voltage conversion transceiver of the brand specification, so that the external network device can transmit network information with the electronic device automatically.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 8, 2021
    Inventor: YEN-LUNG CHOU
  • Publication number: 20210104411
    Abstract: A SiGe compound etching solution for selectively etching a compound represented by general formula Si1-xGex (provided that x is 0 or more and less than 1) relative to Si, Ge and an oxide thereof, the SiGe compound etching solution including a fluoride and an oxidizing agent, wherein the fluoride includes hexafluorosilicic acid, and an etching rate A as measured under the following conditions is 10 ?/min or more: a blanket substrate having a layer of Si0.75Ge0.25 on the surface thereof is immersed in an etching solution at 25° C., and the etching rate is measured.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 8, 2021
    Inventors: Ming-Yen Chung, Po Ting Chou
  • Publication number: 20210104563
    Abstract: An ultra-thin package structure for an integrated circuit having sensing functions is disclosed. It includes: a first substrate layer, having a first top side and a first bottom side, wherein a plurality of conductive traces are formed on the first top side and the first bottom side; an integrated circuit, having at least one gold-plated die pad on the top side thereof, wherein the at least one gold-plated die pad is connected to the corresponding conductive trace on the first bottom side of the first substrate layer by SMT; a second substrate layer, having a second top side and a second bottom side, wherein a plurality of conductive traces are formed on the second bottom side, and some portions of the conductive traces are covered by solder mask while other portions are exposed externally; and a filling material layer, formed between the first and the second substrate layer with the integrated circuit therebetween.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 8, 2021
    Inventors: Chi-Chou LIN, Zheng Ping HE
  • Publication number: 20210103547
    Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. An apparatus includes a physical layer interface coupled to a serial bus and configurable for a high-speed mode of communication and a low-speed mode of communication, and a rate detector configured to receive a clock signal from the serial bus, and to use a reference clock to determine a unit interval representative of a data rate of the serial bus. The apparatus may also include interval calculation logic configured to determine an interval related to timing of a data signal transmitted on the serial bus, the interval having a duration expressed as a number of cycles of the reference clock. The physical layer interface may be configured to use the interval to capture data in the data signal.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 8, 2021
    Inventors: Yasser AHMED, Ying DUAN, Shih-Wei CHOU
  • Publication number: 20210105852
    Abstract: A method for acquiring system information (SI) performed by a user equipment (UE) in a radio resource control (RRC)_CONNECTED state is provided. The method includes: performing a first set of operations after determining that the UE is not configured with a common search space (CSS) in an active bandwidth part (BWP); and performing a second set of operations after determining that the UE is configured with the CSS in the active BWP. The first set of operations includes: transmitting, to a cell, a first RRC message for requesting a required system information block (SIB) after determining that the required SIB is provided by the cell; and receiving, from the cell, a second RRC message including the required SIB. The second set of operations includes: transmitting, to the cell, a third RRC message for requesting the required SIB after determining that the required SIB is provided by the cell and the required SIB is not broadcast in the cell; and receiving, from the cell, the required SIB in the CSS.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 8, 2021
    Inventors: MEI-JU SHIH, HUNG-CHEN CHEN, CHIE-MING CHOU
  • Patent number: D916371
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 13, 2021
    Inventor: Eric Chou