Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.

Abstract: A topical formulation comprising (a) a therapeutically effective amount of tofacitinib; (b) at least one solvent; and (c) optionally one or more other pharmaceutically acceptable excipients is provided. Also provided is a method for treating and/or preventing autoimmune diseases in a subject administering said topical formulation.

Abstract: A keycap forming method includes the following steps. Firstly, a stabilizer bar is fixed on a first male mold. Then, a keycap is formed through a second male mold and a female mold according to an injection molding process. Then, the second male mold and the female mold are separated from each other, so that the keycap is fixed on the female mold. Then, the first male mold and the female mold are stacked on each other, so that the stabilizer bar and the keycap are combined together. Then, the first male mold and the female mold are separated from each other. Consequently, the stabilizer bar is detached from the first male mold. By using the keycap forming method, it is not necessary to manually assemble the stabilizer bar with the keycap.

Abstract: A method of making a maxillary tray appliance comprises obtaining a first virtual model of an edentulous maxillary gum of a patient, and obtaining a virtual component, where the virtual component comprises a virtual contacting surface. The method further comprises receiving the first virtual model, aligning the first virtual model or the virtual component in 3D space, generating a virtual tray appliance, and fabricating a maxillary tray appliance using the virtual tray appliance.

Abstract: Systems and methods of managing creation and configuration for 5G networks, NFs and NSSIs are provided. An instantiation or configuration request received from a managed entity respectively instantiates or configures the appropriate element. For NF instantiation, when the NF has a virtualized part to be instantiated by a VNF, interaction with an NFV MANO system instantiates the VNF is followed by NF instantiation notification and MOI creation for the NF. For NF configuration, the NF is configured and notification provided thereof. For network instantiation, after reception of a network creation request, interaction with the system to instantiate a NS that realizes the network is followed by determination that a new VNF associated with the NS has been instantiated, creation of a NF (constituting the network) MOI is realized by the new VNF, and NF configuration. For NSSI creation, a NF constituting the NSSI is created and configured.

Abstract: An insole design method and an insole design system are provided, and the method includes: capturing an uncompressed free foot model by a depth camera and obtaining a free foot model three-dimensional image; capturing a pressed foot model stepped on a transparent pedal by the depth camera and obtaining a pressed foot model three-dimensional image; aligning the free foot model three-dimensional image with the pressed foot model three-dimensional image; calculating and obtaining a plantar deformation quantity according to the aligned free foot model three-dimensional image and the aligned pressed foot model three-dimensional image; and completing the designed insole according to a sole projection plane or a three-dimensional profile of the specific sole and the plantar deformation quantity.

Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.

Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. In some embodiments, a ventilation trench and an isolation trench are concurrently within a capping substrate. The isolation trench isolates a silicon region and has a height substantially equal to a height of the ventilation trench. A sealing structure is formed within the ventilation trench and the isolation trench, the sealing structure filing the isolation trench and defining a vent within the ventilation trench. A device substrate is provided and bonded to the capping substrate at a first gas pressure and hermetically sealing a first cavity associated with a first MEMS device and a second cavity associated with a second MEMS device. The capping substrate is thinned to open the vent to adjust a gas pressure of the second cavity.

Abstract: Devices and methods of providing performance measurements (PMs) for Network Function Virtualization are generally described. A Virtual Network Function (VNF) PM job is scheduled at a VNF and VNF PM data received in response. From the VNF PM data, it is determined that virtualized resource (VR) management may be a cause of poor VNF performance. A VR PM job is scheduled and results in VR PM data. The VR PM and VNF PM data are analyzed to determine whether to increase the VR at the VNF. If an increase is determined, a request for the increase is transmitted from an element manager to a VNF manager or the VNF PM and/or VR PM data are provided to a Network Manager (NM) for the NM to request the increase by a Network Function Virtualization Orchestrator (NFVO).

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

Abstract: An image generating method and an electronic apparatus are provided. The method includes: determining whether at least one object in a plurality of first images to be captured will generate a blur to generate a determination result; determining a first amount of at least one second image in the plurality of first images and a second amount of at least one third image in the plurality of first images according to the determination result, wherein a first setting for capturing the second image is different from a second setting for capturing the third image; capturing the second image according to the first setting; capturing the third image according to the second setting; using the first amount of the second image and the second amount of the third image to perform an image superposition operation to generate an output image; and outputting the output image.

Abstract: An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.

Abstract: A power controller for use in a PFC power converter is capable being immune from audible noise during the test of load transient response. A transconductor with a transconductance compares an output voltage of the PFC power converter with a target voltage to provide a compensation current, which builds up a compensation voltage. An ON-time controller is configured to end an ON time of a power switch in response to the compensation voltage. An OFF-time controller is configured to end an OFF time of the power switch. A compensation-voltage designator presets the compensation voltage. A status detector controls the transconductor, the ON-time controller, the OFF-time controller, and the compensation-voltage designator, in response to the output voltage, a top-boundary voltage and a bottom-boundary voltage.

Abstract: A molecular probe includes a detector molecule specific to a target molecule, and at least one label linked covalently or non-covalently to the detector molecule. The label includes a catalyst for generating electrons and/or mediators from a solution. The catalyst includes a nanomaterial, an enzyme, a metal, and/or a metal complex. The mediators can accumulate in the solution for a period of time. The detector molecule and the target molecule interact with each other by a protein based or nucleotide sequence based interaction. The mediators participate in a chemical reaction that generates a signal that may be a change in optical, electromagnetic, thermodynamic or mechanical properties. Generation efficiency of the mediators is enhanced by providing an energy to the solution. The molecular probe may be used with a molecular detection assay performed on a surface. A method for assaying the target molecule using the molecular probe is also provided.

Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

Abstract: A delay-locked loop includes a phase detector configured to detect a phase difference between a first clock and a second clock, a charge pump configured to increase a charge amount at a capacitive load in accordance with a first charge amount and decrease the charge amount at the capacitive load in accordance with a second charge amount based on a phase difference provided by the phase detector, a sample and hold circuit configured to receive the charge amount from the capacitive load and hold the charge amount, and a voltage control delay line configured to select a delay amount based on the charge amount received from the sample and hold circuit. At least one parameter of the delay-locked loop is configured such that a desired pump current ratio of a delay cell is achieved by adjusting a delay amount of the delay cell and/or an amount of current coupled to the delay cell.

Abstract: A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.