Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adjusting power limit in electronic apparatus based on self-power consumption time averages of battery
    Patent number: 12045108
    Abstract: An electronic apparatus and a load adjusting method thereof are provided. The method includes the following steps. Powering of an external power supply is detected. A self-power consumption time of the battery from a full capacity to a preset capacity is calculated and recorded when the powering of the external power supply is detected. A first average value of multiple self-power consumption times recorded within a preset period from a current time is calculated, and the first average value is compared with a second average value of the self-power consumption times of a previous preset period of the preset period. A value of a power limit for controlling the electronic apparatus to enter a load adjusting state is adjusted according to a comparison result.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: July 23, 2024
    Assignee: Acer Incorporated
    Inventors: Shuo-Jung Chou, Chuan-Jung Wang, Chih-Chiang Chen
  • Surface oxidation control of metal gates using capping layer
    Patent number: 12046475
    Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Chou, Tze-Liang Lee
  • Method for processing carbon fiber bundle
    Patent number: 12043955
    Abstract: Disclosed is a method for processing a carbon fiber bundle, which can adjust bundling property, winding property and wear resistance of sizing fibers. The method includes following steps: (i) coating a sizing agent on at least one carbon fiber bundle, in which the sizing agent includes a thermoplastic resin; (ii) drying the carbon fiber bundle by hot air; and (iii) heating the carbon fiber bundle by an infrared light, in which a heating temperature of the heating is equal to or higher than a melting point of the thermoplastic resin.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: July 23, 2024
    Assignee: FORMOSA PLASTICS CORPORATION
    Inventors: Long-Tyan Hwang, Sheng-Shiun Lin, Yu-Sheng Li, Ching-Cheng Chung, Cheng-Chun Chou
  • Processing of synchronization barrier instructions
    Patent number: 12045615
    Abstract: A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: July 23, 2024
    Assignee: Apple Inc.
    Inventors: Deepankar Duggal, Kulin N Kothari, Mridul Agarwal, Chang Xu, Yanran Yang, Richard F Russo, Yuan C Chou, Douglas C Holman
  • Rapid bio/chemical assay
    Patent number: 12044603
    Abstract: The present invention is related to the field of bio/chemical sampling, sensing, assays and applications. Particularly, the present invention is related to how to make the sampling/sensing/assay become simple to use, fast to results, highly sensitive, easy to use, using tiny sample volume (e.g. 0.5 uL or less), operated by a person without any professionals, reading by mobile-phone, or low cost, or a combination of them.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: July 23, 2024
    Assignee: Essenlix Corporation
    Inventors: Stephen Y. Chou, Wei Ding
  • Heat dissipation structures
    Patent number: 12046528
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • PVD SYSTEM AND COLLIMATOR
    Publication number: 20240240306
    Abstract: A physical vapor deposition (PVD) system includes: a pedestal configured to accommodate a semiconductor wafer; a cover plate above the pedestal configured to hold a target; and a collimator disposed above the pedestal and below the cover plate. The collimator has an upper surface and a lower surface. The lower surface is flat, and the upper surface is non-flat. A first thickness, in a vertical direction, of the collimator at a central portion is smaller than a second thickness, in the vertical direction, of the collimator at a peripheral portion.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 18, 2024
    Inventors: Kuan-Lin Chen, Tsung-Yi Chou, Wei-Der Sun, Hao-Wei Kang
  • METHOD FOR GLYCOPROTEIN MODIFICATION
    Publication number: 20240238432
    Abstract: A method for modifying glycoproteins is provided. The present disclosure also provides a method for producing glycoprotein-payload conjugates, the conjugates produced thereby, and the use thereof.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 18, 2024
    Inventors: Shih-Hsien CHUANG, Yu-Wei LAI, Cheng-Chou YU, Shu-Ping YEH, Jin-Yu WANG, Shih-Chong TSAI, Wei-Ting SUN, Chin-Yi Huang
  • METHOD AND APPARATUS FOR MANAGING INTER-RAT CAPABILITY OF USER EQUIPMENT UNDER DISASTER SITUATION
    Publication number: 20240244506
    Abstract: A method for managing inter-radio access technology (inter-RAT) capability of a user equipment (UE) includes: receiving system information broadcasted from a public land mobile network (PLMN), wherein the system information is indicative of a disaster condition of the PLMN, and the UE is currently camps on a first RAT of the PLMN; and in response to receiving the system information, performing a PLMN search operation to camp on a second RAT of the PLMN, and performing an inter-RAT management operation to prevent the UE from transiting to the first RAT of the PLMN.
    Type: Application
    Filed: November 7, 2023
    Publication date: July 18, 2024
    Applicant: MEDIATEK INC.
    Inventors: Shuang-An Chou, Cheng-Hsiao KO, Yu-Hsiu Tseng, Kuang-Ting Cheng
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240244834
    Abstract: A semiconductor device, including a first MOS device, a second MOS device, a first dielectric layer, a stop layer, and a second dielectric layer, is provided. The first MOS device and the second MOS device are located on a substrate. The first dielectric layer is beside the first MOS device and the second MOS device. The stop layer is disposed on the first dielectric layer. The second dielectric layer covers the stop layer. The thickness of the second dielectric layer above the first MOS device is greater than the thickness of the second dielectric layer above the second MOS device.
    Type: Application
    Filed: January 16, 2023
    Publication date: July 18, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Mei-Yuan Chou, Yoshinori Tanaka
  • CHARGING FOR EDGE ENABLING INFRASTRUCTURE RESOURCES
    Publication number: 20240243936
    Abstract: Various embodiments herein relate to a logical element configured to consume a management service (MnS). The logical element may further identify, based on consumption of the MnS, a performance measurement related to usage of an edge enabling infrastructure resource for an edge application server (EAS); generate, based on the performance measurement, charging data related to the edge enabling infrastructure; and transmit an indication of the charging data to a second logical clement of the cellular system. The logical element may further identify, based on the transmitted indication of the charging data, a Charging Data Response received from the second logical element. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 12, 2022
    Publication date: July 18, 2024
    Inventors: Yizhi YAO, Joey CHOU
  • OPTICAL DIGITAL-TO-ANALOG CONVERTER
    Publication number: 20240241425
    Abstract: The present disclosure relates to an optical digital-to-analog converter (DAC). The optical DAC includes a first waveguide path configured to receive a first optical signal and a second waveguide path configured to receive a second optical signal. A first phase shifter segment interfaces with the first and second waveguide paths. The first phase shifter segment is configured to selectively generate a first phase shift between the first optical signal and the second optical signal in response to a first digital input. A second phase shifter segment interfaces with the first and second waveguide paths. The second phase shifter segment is configured to selectively generate a second phase shift between the first optical signal and the second optical signal in response to a second digital input. The first digital input and the second digital input correspond to different bits of a digital signal.
    Type: Application
    Filed: April 19, 2023
    Publication date: July 18, 2024
    Inventors: Ming Yang Jung, Chewn-Pu Jou, Lan-Chou Cho, Stefan Rusu, Cheng-Tse Tang, Tai-Chun Huang, You-Cheng Lu
  • Power Control in a Computing Device
    Publication number: 20240241560
    Abstract: A computing device permits distribution of power received from an external power source to one or more subsystems of the computing device. The computing device receives input requesting a power control operation and, responsive to the input, interrupts the distribution of the power to at least one of the subsystems.
    Type: Application
    Filed: January 16, 2023
    Publication date: July 18, 2024
    Inventors: Hsuan Wei-Yi, Yi-Hsin Huang, Ying-Chi Chou, Wen-Fu Tsai
  • METHODS AND APPARATUSES FOR COLLISION CONTROL OF SIDELINK COMMUNICATIONS IN WIRELESS COMMUNICATION SYSTEM
    Publication number: 20240244545
    Abstract: A method performed by a wireless communication device includes determining whether to transmit a first Sidelink Synchronization Signal (SLSS) according to a priority parameter when an occasion of the first SLSS collides with a Physical Sidelink Feedback Channel (PSFCH) that carries Sidelink Feedback Control Information (SFCI). The priority parameter is associated with a Physical Sidelink Shared Channel (PSSCH) that corresponds to the PSFCH.
    Type: Application
    Filed: February 9, 2024
    Publication date: July 18, 2024
    Inventors: Yu-Hsin Cheng, Tsung-Hua Tsai, Chie-Ming Chou, Yung-Lan Tseng
  • CAPACITOR AND METHOD FOR FORMING THE SAME
    Publication number: 20240243165
    Abstract: A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Tao CHOU, Chee-Wee LIU
  • IMAGE SENSING DEVICE AND IMAGE SENSING METHOD
    Publication number: 20240242529
    Abstract: The present invention provides an image sensing device and an image sensing method. The image sensing device comprises an image sensing array and an image processing circuit. The image sensing array obtains a first frame for a test object, and the first frame comprises a plurality of first pixel values. The image processing circuit analyzes the first frame, and generate an overexposure area for the first pixel values greater than a first threshold in the first frame. Then, the image sensor array obtains a second frame for the overexposure area, and the second frame comprises a plurality of second pixel values. The image processing circuit performs a detection processing on all the first pixel values in the first frame, which retains the first pixel values outside of the overexposure area in the first frame, and replaces the first pixel values in the overexposure area with the second pixel values.
    Type: Application
    Filed: October 25, 2023
    Publication date: July 18, 2024
    Inventors: Ping-Hung Yin, Chia-Cheng Yang, Yung-Ming Chou, Pei-Ting Tsai
  • POWER SUPPLY SYSTEM AND FUEL CELL POWER GENERATION PERFORMANCE DETECTION DEVICE AND CONTROL METHOD THEREOF
    Publication number: 20240241179
    Abstract: A power supply system, a fuel cell power generation performance detection device and a control method thereof are provided. The fuel cell has a rated output voltage and an internal resistance having a preset resistance value. The detection device includes a test resistor, a first test switch, a current detection unit and a control unit. The control unit controls the first test switch and the current detection unit to send a first control signal to selectively turn on the first test switch. When the first test switch is turned on, the fuel cell, the test resistor, the first test switch and the current detection unit define a test loop. The current detection unit detects a test current passing through the test loop. The control unit obtains a real-time resistance value of the internal resistance based on the test current to evaluate the power generation performance of the fuel cell.
    Type: Application
    Filed: November 1, 2023
    Publication date: July 18, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuh-Fwu CHOU, Ching-Jung LIU, Yin-Wen TSAI, Ku-Yen KANG, Chih-Wei HSU
  • METHOD AND PHARMACEUTICAL COMPOSITION FOR RESCUING RETINAL DEGENERATION
    Publication number: 20240238334
    Abstract: The present invention provides a method for rescuing retinal degeneration comprising administering a subject in need thereof a pharmaceutical composition comprising an inhibitor of DUSP6 via ERK 1/2 autophagy pathway.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Applicant: Taipei Veterans General Hospital
    Inventors: Shih-Hwa Chiou, Shih-Jie Chou, Yueh Chien, Yi-Ping Yang
  • CONNECTING STRUCTURE AND SIGNAL TRANSMISSION SYSTEM
    Publication number: 20240243527
    Abstract: A connecting structure includes a flexible flat cable. The flexible flat cable includes a first end portion, a second end portion, a connecting portion, a first pad region, a second pad region and a slot. The connecting portion is connected between the first end portion and the second end portion. The first pad region is disposed on the first end portion. The second pad region is disposed on the second end portion. The slot is formed in the connecting portion. The slot is extended along a length direction of the flexible flat cable. The flexible flat cable is a laminated structure including at least one set of signal trace pattern and at least one shielding structure. The at least one shielding structure correspondingly surrounds the at least one set of signal trace pattern in the connecting portion.
    Type: Application
    Filed: January 16, 2024
    Publication date: July 18, 2024
    Applicant: CYNTEC CO., LTD.
    Inventors: Shih-Hsien Tseng, Sheng-Ju Chou, Ming-Feng Chiang
  • INDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20240243163
    Abstract: The present disclosure provides a semiconductor structure including a vertical inductor. The semiconductor structure includes a first semiconductor substrate, a first conductive layer, a first magnetic layer, and a second magnetic layer. The first semiconductor substrate has a top surface, and the first conductive layer is vertically inserted into the first semiconductor substrate from the top surface of the first semiconductor substrate. The first magnetic layer is disposed in the first semiconductor substrate and surrounds the first conductive layer. The second magnetic layer is disposed over the first conductive layer and the first magnetic layer.
    Type: Application
    Filed: January 13, 2023
    Publication date: July 18, 2024
    Inventors: WEI-YU CHOU, YANG-CHE CHEN, CHI-HUI LAI, YI-LUN YANG, HSIANG-TAI LU