Abstract: An annular optical element includes an outer annular surface, an inner annular surface, a first side surface, a second side surface and a plurality of strip-shaped wedge structures. The outer annular surface surrounds a central axis of the annular optical element and includes at least two shrunk portions. The first side surface connects the outer annular surface and the inner annular surface. The second side surface connects the outer annular surface and the inner annular surface, wherein the second side surface is disposed correspondingly to the first side surface. The strip-shaped wedge structures are disposed on the inner annular surface, wherein each of the strip-shaped wedge structures is disposed along a direction from the first side surface towards the second side surface and includes an acute end and a tapered portion connecting the inner annular surface and the acute end.

Abstract: The disclosure provides an electronic device with a vibration function and a vibration driving method. The electronic device includes a processor and an audio player. The processor outputs an audio signal according to an application program, and executes an audio analysis module to analyze the audio signal. The audio player is coupled to the processor, and receives the audio signal. When the audio analysis module determines that the audio signal has a loudness with an audio frequency lower than a default frequency threshold according to an audio frequency distribution of the audio signal, the audio analysis module outputs a vibration drive signal according to the loudness of the audio signal.

Abstract: A conduit system for transporting gas from a gas containing chamber for processing a substrate from which semiconductor devices are formed includes a liner with a spiral vent. The conduit system utilizes a curtain of gas to prevent or reduce deposition of material onto an inner surface of the conduit transporting the gas from the gas containing chamber.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width.

Abstract: The subject disclosure relates to techniques for detecting an object. A process of the disclosed technology can include steps for receiving three-dimensional (3D) Light Detection and Ranging (LiDAR) data of the object at a first time, generating a first point cloud based on the 3D LiDAR data at the first time, receiving 3D LiDAR data of the object at a second time, generating a second point cloud based on the 3D LiDAR data at the second time, aggregating the first point cloud and the second point cloud to form an aggregated point cloud, and placing a bounding box around the aggregated point cloud. Systems and machine-readable media are also provided.

Abstract: Techniques discussed herein can facilitate edge computing in connection with a variety of deployment scenarios. Various embodiments can facilitate one or more of: deploying UPF(s) (User Plane Function(s)) to support edge computing; removing UPF(s) not needed for edge computing; deploying local DN(s) (Data Network(s)); E2E (Edge-to-Edge) OSS (Operations Support System) deployment scenarios; and providing RAN (Radio Access Network) condition data to support various applications (e.g., autonomous driving).

Abstract: An aluminum alloy material includes 1.0 wt % to 13.0 wt % of Si, 0.2 wt % to 1.4 wt % of Fe, 0.2 wt % to 0.8 wt % of Ni, and the remainder being Al and inevitable impurities. The aluminum alloy material can be 3D printed or die-casted to form an aluminum alloy object with a high thermal conductivity.

Abstract: A matrix computing device and an operation method for the matrix computing device are provided. The matrix computing device includes a storage unit, a control circuit, and a computing circuit. The storage unit includes a weight matrix. The control circuit re-orders an arrangement order of weights in the weight matrix according to a shape of an output matrix to determine a weight readout order of the weights. The computing circuit receives the weights based on the weight readout order, and performs a matrix computation on the weights and an input matrix to generate a computing matrix. The control circuit performs a reshape transformation on the computing matrix to generate the output matrix, and writes the output matrix to the storage unit.

Abstract: An optical path folding element includes a main body, a light absorption film layer and a matte structure. The main body has optical surface including an incident surface, a reflective surface and an emitting surface. A light enters into the optical folding element through the incident surface. The reflective surface reflects the light so as to change a traveling direction thereof. The light exits the optical folding element through the emitting surface. The light absorbing film layer is configured to reduce reflectance and provided adjacent to at least part of the optical surface, and the light absorbing film layer is in physical contact with the main body. The matte structure is disposed adjacent to at least part of the optical surface. The matte structure provides an undulating profile on a surface of the optical path folding element, and the matte structure is formed in one-piece with the main body.

Abstract: A rails assembly includes outer and inner rails, an elastic assembly, a hook member. The outer and inner rails are provided with first and second opening portions. The inner rail is disposed on the outer rail. The elastic assembly is disposed on the inner rail. The hook member is connected to the inner rail and opposite to the second opening portion. When the hook member is located at a first position by sliding the inner rail relative to the outer rail, the hook member is pushed by the elastic assembly to pass through the second opening portion. When the hook member is located at a second position in the same manner, the second and first opening portions are opposite to each other and the hook member is pushed by the elastic assembly to pass through the second and first opening portions. An electronic equipment including the rails assembly is provided.

Abstract: In some embodiments, the present disclosure relates to an integrated chip fabrication device. The device includes a stealth laser apparatus arranged over a chuck configured to hold a substrate. An infrared camera is arranged over the chuck and configured to detect an alignment mark below the substrate. The alignment mark is used to align the stealth laser apparatus over the chuck. Control circuitry is configured to operate the stealth laser apparatus to form a stealth damage region at a location within the substrate that is determined based upon the alignment mark. The stealth damage region separates an inner region of the substrate from an outer region of the substrate.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Abstract: Techniques for performance measurements related to application triggering and short message service (SMS) over non-access stratum (NAS) including obtaining raw performance measurements from one or more network functions in a wireless communication network, the one or more network functions including at least one of a network exposure function (NEF) or an access and mobility management function (AMF), and generating performance measurements for the one or more network functions based on the raw performance measurements.

Abstract: A homogeneous composite substrate includes a woven cloth and at least one fiber membrane. The woven cloth includes a plurality of first fibers. The fiber membrane is disposed on at least one surface of the woven cloth, and the fiber membrane includes a plurality of second fibers, in which a material of the first fibers and a material of the second fibers are the same, a fiber diameter of each first fiber is larger than or equal to 20 ?m and smaller than or equal to 130 ?m, and a fiber diameter of each second fiber is larger than or equal to 3 ?m and smaller than or equal to 10 ?m.

Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.

Abstract: A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Abstract: The present disclosure relates to utilizing a firmware configuration system to efficiently update a firmware profile configuration of computing devices (e.g., host devices in a datacenter). For example, the firmware configuration system facilitates updating the firmware profile configuration, such as for a Unified Extensible Firmware Interface (UEFI) profile and/or a Basic Input/Output System (BIOS), without needing to develop, deploy, and install a new BIOS. More specifically, the firmware configuration system updates (e.g., via a baseband management controller) firmware profile configurations by modifying a profile configuration table in flash memory (i.e., on an SPI flash-based chip) of a BIOS with a firmware profile configuration update patch and without affecting other parts of the BIOS.

Abstract: A data recovery method for a memory device is disclosed. The memory device has a target memory cell, a target word line and an adjacent word line, the adjacent word line is adjacent to the target word line. The target word line is connected to a gate of the target memory cell. The adjacent word line is connected to a gate of an adjacent memory cell, and the adjacent memory cell is adjacent to the target memory cell. The data recovery method includes the following steps. Applying a first program voltage to the target memory cell through the target word line. When applying the first program voltage, concurrently applying a second program voltage to the adjacent memory cell through the adjacent word line.

Abstract: An antenna module is provided, in which an antenna supporting substrate having a step-shaped hollow cavity is disposed on a circuit structure having an antenna part, so that the antenna part is exposed from the step-shaped hollow cavity, and an antenna structure is arranged on the steps of the step-shaped hollow cavity to cover the antenna part and is electromagnetically coupled with the antenna part, and there is no barrier but an air medium between the antenna structure and the antenna part.