Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

Abstract: A passive millimeter wave imaging system that includes at least one millimeter wave frequency scanning antenna and multiple beam formers collecting narrow beams of millimeter wave radiation from a two-dimensional field of view. The collected radiation is amplified and separated into bins corresponding to various vertical and horizontal beam orientations. In a preferred embodiment each beam formers include one phase processor with 232 inputs and 192 outputs that feed into 192 frequency processors. In another preferred embodiment each beam formers include one phase processor with 232 inputs and 72 outputs that feed into only 24 frequency processors. In this second embodiment 26 3×1 PIN diode switches sequentially switch one of three phase processor outputs into a frequency processor. As in the first embodiment two dimensional images of a target are obtained by the simultaneous detection of signal power within each beam and converting it into pixel intensity level.

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout.

Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

Abstract: A retractor for manipulating an object includes a body having proximal and distal ends, a retraction device, and an actuation device. The retraction device has a head connected to the distal end of the body, substantially rigid needles, and an actuator. The head has a pivot. The needles are pivotally connected to the head about the pivot. The actuator is operatively connected to the needles and is movably disposed within the head and/or the body. The actuation device is connected to the proximal end of the body. The actuation device is operatively connected to the actuator through the body and, upon actuation thereof, moves the actuator to selectively rotate the needles between a stowed position where the needles are stowed within the head and a fully extended position where the needles are extended out of the head.

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

Abstract: A lead frame assembly includes at least two layers, each including an electrically conductive bus and a group of leads that extend substantially from a first edge of the assembly. The leads of each layer may include portions that extend in substantially the same direction. The electrically conductive buses are at least partially superimposed with respect to one another. Leads of one of the layers may be arranged in groups which flank the remainder of the lead of another layer. A dielectric element is disposed at least partially between the layers; for example, between at least portions of the superimposed regions of the buses. One of the buses may be connectable to a power supply source (Vcc), while the other may be connectable to a power supply ground (Vss). In such an arrangement, the mutually superimposed regions of the buses may form a decoupling capacitor.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A surgical stapler comprises a hollow shaft 10 and a tube 92 slidable axially within the shaft between a forward position wherein one end 96 of the tube projects beyond a free end of the shaft to enter a puncture site in a blood vessel and a rearward position wherein the end of the locator tube is retracted within the shaft. A surgical staple 40 straddles the tube 92 and is slidable thereon forwardly towards an anvil 24 against which the staple may be deformed to staple together the opposite edges of the puncture site. A cam mechanism drives the staple forwardly along the tube 92 into deforming engagement with the anvil and at the same time retracts the tube into the shaft in time to allow the legs of the staple to close onto the puncture site.

Abstract: A surgical stapler comprises a hollow shaft 10 and a tube 92 slidable axially within the shaft between a forward position wherein one end 96 of the tube projects beyond a free end of the shaft to enter a puncture site in a blood vessel and a rearward position wherein the end of the locator tube is retracted within the shaft. A surgical staple 40 straddles the tube 92 and is slidable thereon forwardly towards an anvil 24 against which the staple may be deformed to staple together the opposite edges of the puncture site. A cam mechanism drives the staple forwardly along the tube 92 into deforming engagement with the anvil and at the same time retracts the tube into the shaft in time to allow the legs of the staple to close onto the puncture site.

Abstract: Die-cut blanks for forming folding cartons and corresponding cartons for housing sheeted cleaning articles, particularly for dryer sheets, are disclosed. The blanks and cartons include a fully enclosed access flap and lapping glue flap.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.