Abstract: Disclosed is a non-contact optical measurement device for detecting or measuring different geometric workpiece features based on configurable light-propagation paths of light emitted from a light source and reflected by a workpiece surface for incidence upon a spectral sensor. The light-propagation paths are configurable based on which optical probe is attached to a rotation stage that rotates the probe about an optical axis and in a collimated region.

Abstract: Apparatuses, systems and methods associated with a metrology system for high-speed, non-contact coordinate measurements of parts are disclosed herein. In embodiments, the metrology system includes a metrology bridge to be coupled to a measurement assembly. The measurement assembly may include a stage moveable across multiple independent axes. The bridge may include a housing, mounting members coupled to the housing, and a plurality of sensors mounted within the housing. The mounting members may rotatably couple the housing to the measurement assembly. Further, sensor elements of the plurality of sensor devices may be aligned along a length of the housing and may be directed out of the housing.

Abstract: Disclosed is a non-contact optical measurement device for detecting or measuring different geometric workpiece features based on configurable light-propagation paths of light emitted from a light source and reflected by a workpiece surface for incidence upon a spectral sensor. The light-propagation paths are configurable based on which optical probe is attached to a rotation stage that rotates the probe about an optical axis and in a collimated region.

Abstract: Apparatuses, systems and methods associated with a metrology system for high-speed, non-contact coordinate measurements of parts are disclosed herein. In embodiments, the metrology system includes a metrology bridge to be coupled to a measurement assembly. The measurement assembly may include a stage moveable across multiple independent axes. The bridge may include a housing, mounting members coupled to the housing, and a plurality of sensors mounted within the housing. The mounting members may rotatably couple the housing to the measurement assembly. Further, sensor elements of the plurality of sensor devices may be aligned along a length of the housing and may be directed out of the housing.

Abstract: Apparatuses, systems and methods associated with a metrology system for high-speed, non-contact coordinate measurements of parts are disclosed herein. In embodiments, the metrology system includes a metrology bridge to be coupled to a measurement assembly. The measurement assembly may include a stage moveable across multiple independent axes. The bridge may include a housing, mounting members coupled to the housing, and a plurality of sensors mounted within the housing. The mounting members may rotatably couple the housing to the measurement assembly. Further, sensor elements of the plurality of sensor devices may be aligned along a length of the housing and may be directed out of the housing.

Abstract: Apparatuses, systems and methods associated with a metrology system for high-speed, non-contact coordinate measurements of parts are disclosed herein. In embodiments, the metrology system includes a metrology bridge to be coupled to a measurement assembly. The measurement assembly may include a stage moveable across multiple independent axes. The bridge may include a housing, mounting members coupled to the housing, and a plurality of sensors mounted within the housing. The mounting members may rotatably couple the housing to the measurement assembly. Further, sensor elements of the plurality of sensor devices may be aligned along a length of the housing and may be directed out of the housing.

Abstract: Apparatuses, systems and methods associated with a metrology system for high-speed, non-contact coordinate measurements of parts are disclosed herein. In embodiments, the metrology system includes a metrology bridge to be coupled to a measurement assembly. The measurement assembly may include a stage moveable across multiple independent axes. The bridge may include a housing, mounting members coupled to the housing, and a plurality of sensors mounted within the housing. The mounting members may rotatably couple the housing to the measurement assembly. Further, sensor elements of the plurality of sensor devices may be aligned along a length of the housing and may be directed out of the housing.

Abstract: A method for selectively depositing a source material on a wafer is disclosed. In one embodiment, a wafer is having at least one recessed feature is provided. A top surface of the wafer is then coated with an inhibiting material. Finally, a source material is selectively deposited in the at least one recessed feature, the source material repelled by the inhibiting material. In another embodiment, the inhibiting material is one of a wax, a surfactant or an oil.

Abstract: A method for selectively depositing a source material on a wafer is disclosed. In one embodiment, a wafer is having at least one recessed feature is provided. A top surface of the wafer is then coated with an inhibiting material. Finally, a source material is selectively deposited in the at least one recessed feature, the source material repelled by the inhibiting material. In another embodiment, the inhibiting material is one of a wax, a surfactant or an oil.

Abstract: A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.

Abstract: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.

Abstract: According to one aspect of the present invention, a method of electrochemically polishing a semiconductor substrate may be provided. A semiconductor substrate processing fluid, having a plurality of abrasive particles therein, may be placed between the surface of the semiconductor substrate and the polish head. The polish head may be moved relative to the surface of the semiconductor substrate to cause the abrasive particles to polish the surface of the semiconductor substrate. According to a second aspect of the present invention, a method for electro-polishing a semiconductor substrate may be provided. A semiconductor substrate may be placed in an electrolytic solution. A surface of the semiconductor substrate may be contacted with at least one conductive member. A voltage may be applied across the electrolytic solution and the at least one conductive member. The at least one conductive member may be moved across the surface of the semiconductor substrate.

Abstract: The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising at least one opening, and then applying a nanotube slurry comprising at least one nanotube to the substrate, wherein the at least one nanotube is substantially placed within the at least one opening.

Abstract: A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used relative to an etch stop layer abutting a transistor gate. This allows the first CMP step to stop after contacting the etch stop layer, which results in substantially uniform “within die”, “within wafer”, and “wafer to wafer” topography. The removal step may expose a temporary component, such as a polysilicon gate within the transistor gate structure. Once the polysilicon gate is exposed other processes may be employed to produce a transistor gate having desired properties.

Abstract: A slurry for removing metals, useful in the manufacture of integrated circuits generally, and for the chemical mechanical polishing of noble metals particularly, may be formed by combining periodic acid, an abrasive, and a buffer system, wherein the pH of the slurry is between about 4 to about 8.