Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

Abstract: An electronic structure comprising stacks comprising alternating dielectric materials and conductive materials in a cell region of the electronic structure. A pillar high-k dielectric material is adjacent to the stacks and in a pillar region of the electronic structure. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material in the pillar region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials in the cell region of the electronic structure. The cell high-k dielectric material adjoins a portion of the pillar high-k dielectric material. Additional electronic structures are disclosed, as are related electronic devices, systems, and methods of forming an electronic device.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.

Abstract: A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

Abstract: Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric harrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric harrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.