Abstract: Designs of controllers for flash memory array are described. A controller is designed to form data packs of a predefined size with compressed data segments in different sizes. The data packs are encoded with ECC in two dimensions. When the data packs are read out, the ECC is applied in two dimensions to detect and correct errors that can be corrected by the ECC.

Abstract: Designs of controllers for flash memory array are described. A controller is designed to form data packs of a predefined size with compressed data segments in different sizes. The data packs are encoded with ECC in two dimensions. When the data packs are read out, the ECC is applied in two dimensions, possibly repeated, to detect and correct errors that can be corrected by the ECC.

Abstract: Techniques for Implementation of keeping data integrity in multiple dimensions are described. A single but relatively complicated engine is used to encode a line of original data bits in one dimension once and for all, while a linear array of simple engines are used in another dimension to keep revising sets of redundant data bits for successive lines of original data bits, where the redundant data bits become final when a last line of original data bits is accessed.

Abstract: Designs of integrated modules for securing data are described. According to one aspect of the present invention, a data set is distributed among a plurality of data channels, each of the data channels including an encrypting/decrypting module designed to process a data stream or set. Modules in the data channels work independently from each other. A next data stream is timely provided to a data channel when a current data stream is about to finish, resulting in increased efficiency when encrypting data from a source or decrypting encrypted data for a source.

Abstract: Designs of persistently managing mapping tables are described. To keep the performance of writing data into or reading out data from a storage device, such as flash memory, RAM (Random Access Memory) is often used to manage the mapping tables. To prevent the mapping tables from being damaged for whatever reason (e.g., power failure), MRAM (Magnetic RAM) is employed to keep the mapping tables in magnetic domains while the RAM is only used for updating the content of the mapping tables. Not only is the capacity for RAM is significantly reduced, the mapping tables are securely maintained in MRAM and available to RAM while data is being written into or read out from the storage device.

Abstract: A technique of extending a correction limit defined by an ECC is described. According to one aspect of the present invention, remaining errors that cannot be corrected by the ECCs in a data array is first identified and then formed in form of matrix with defined size. These remaining errors are flipped in value, namely from “1” to “0” or “0’ to “1” if the number of the errors are within a range or additional ECCs are applied to correct the errors in flipped data bits.

Abstract: A card reader controller engine includes an interface controller responsive to information. The engine is coupled to the interface controller and is configured to compress the information before the information is to be stored in a memory card. A master interface is coupled to the engine and is further responsive to the compressed information for storage in the memory card.

Abstract: A card reader controller engine includes an interface controller responsive to information. The engine is coupled to the interface controller and is configured to compress the information before the information is to be stored in a memory card. A master interface is coupled to the engine and is further responsive to the compressed information for storage in the memory card.

Abstract: A card reader controller engine includes an interface controller responsive to information. The engine is coupled to the interface controller and is configured to compress the information before the information is to be stored in a memory card. A master interface is coupled to the engine and is further responsive to the compressed information for storage in the memory card.

Abstract: A card reader system includes a card reader controller engine in communication with a Peripheral Component Interconnect Express (PCIe) host and one or more Serial Advanced Technology Attachment (SATA) hard disk drives (HDDs). The card reader controller engine includes a PCIe controller responsive to information from a PCIe host, an engine coupled to the PCIe controller that compresses the information before the information is stored in the SATA HDDs. The card reader controller engine further includes SATA hosts coupled to the engine and responsive to the compressed information for storage in and retrieval from the SATA HDDs.

Abstract: A storage controller with Universal Flash Storage (UFS) interface includes a series bus controller responsive to information from a first externally-located host, and a microprocessor coupled to the series bus controller and responsive to the information, and one or more UFS host interfaces responsive to the output from the microprocessor and operable to generate information to one or more externally-located UFS devices. The number of externally-located UFS devices is equal to the number of UFS host interfaces, wherein the UFS host devices cause simultaneous communication of at least some of the information to the externally-located UFS devices.

Abstract: A single solid state drive (SSD) includes an SSD controller coupled to send and receive information to and from a host through an interface. The SSD controller includes an embedded RAID controller and a plurality of non-volatile memory modules (NVMs) coupled to the SSD controller. The SSD controller causes storage of the received information in the NVMs and sending of the information from the NVMs under the control of the embedded RAID controller.

Abstract: A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon.

Abstract: A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.

Abstract: A Secure Digital (SD) flash microcontroller includes a memory interface to SRAM or DRAM, a flash-memory interface, and a SD interface to an SD bus. The flash memory can be on a flash bus or on the SD bus. The microcontroller is booted from boot code stored in the flash memory. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM.

Abstract: A method and circuitry for detecting a pattern in received data such as the A1A2 boundary in a SONET frame after deserialization. Two consecutive pluralities of bytes of incoming data are stored and compared with the A1 and A2 values (or bit shifted versions of the A1 and A2 values) until the boundary is detected. The data are then bit shifted so that every byte on the bus is either A2 or A1. A new aligned data bus is then formed such that the last A1 bit occurs on the data bus for a given clock cycle and the first A2 bit occurs on the data bus during the next clock cycle.

Abstract: A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.

Abstract: Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

Abstract: A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.

Abstract: Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.