Abstract: A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.

Abstract: Devices and methods are provided to reduce the wake-up time of a Vertical Cavity Surface Emitting Laser (VCSEL) used in a data communication link. For example, in one aspect, a method for optical communications includes, in an optical communication device including a light-emitting device, applying a bias current to the light-emitting device and transmitting a pulse to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage greater than a highest voltage of the preamble signal or data signal.

Abstract: A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.

Abstract: Devices and methods are provided to reduce the wake-up time of a Vertical Cavity Surface Emitting Laser (VCSEL) used in a data communication link. For example, in one aspect, a method for optical communications includes, in an optical communication device including a light-emitting device, applying a bias current to the light-emitting device and transmitting a pulse to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage greater than a highest voltage of the preamble signal or data signal.

Abstract: Devices and methods are provided to reduce the wake-up time of a Vertical Cavity Surface Emitting Laser (VCSEL) used in a data communication link. For example, in one aspect, a method for optical communications includes, in an optical communication device including a light-emitting device, applying a bias current to the light-emitting device and transmitting a pulse to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage greater than a highest voltage of the preamble signal or data signal.

Abstract: A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.

Abstract: A method, apparatus, and computer program product for measuring a slew rate of a digital high speed repeating signal on-chip including, transforming the rising and the falling edges of the signal into a digital pulse signal each; and selecting the digital pulse signals corresponding either to the rising edge or to the falling edge of the signal. Further the method including converting the selected digital pulse signals into an average DC voltage equivalent to the pulse width of the respective digital pulse signal; as well as converting each DC voltage into a binary value.

Abstract: Devices and methods are provided to reduce the wake-up time of a Vertical Cavity Surface Emitting Laser (VCSEL) used in a data communication link. For example, in one aspect, a method for optical communications includes, in an optical communication device including a light-emitting device, applying a bias current to the light-emitting device and transmitting a pulse to the light-emitting device before transmitting a preamble signal or data signal to the light-emitting device, wherein the pulse has a voltage greater than a highest voltage of the preamble signal or data signal.

Abstract: A method, apparatus, and computer program product for measuring a slew rate of a digital high speed repeating signal on-chip comprising, transforming the rising and the falling edges of the signal into a digital pulse signal each; and selecting the digital pulse signals corresponding either to the rising edge or to the falling edge of the signal. Further the method comprises converting the selected digital pulse signals into an average DC voltage equivalent to the pulse width of the respective digital pulse signal; as well as converting each DC voltage into a binary value.

Abstract: The present disclosure regards adjusting a duty cycle, which includes generating a duty cycle signal having a voltage representing a duty cycle of a clock signal; adjusting a reference voltage generated by an adjustable reference voltage generator to match the duty cycle signal to produce a first matched value; inverting voltage sources of the reference voltage generator; adjusting, while the voltage sources are inverted, the reference voltage to produce a second matched value; and calculating a duty cycle value based on the first and second matched values.

Abstract: The present disclosure regards adjusting a duty cycle, which includes generating a duty cycle signal having a voltage representing a duty cycle of a clock signal; adjusting a reference voltage generated by an adjustable reference voltage generator to match the duty cycle signal to produce a first matched value; inverting voltage sources of the reference voltage generator; adjusting, while the voltage sources are inverted, the reference voltage to produce a second matched value; and calculating a duty cycle value based on the first and second matched values.

Abstract: A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.

Abstract: An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream.

Abstract: A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.

Abstract: A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.

Abstract: A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.

Abstract: A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.

Abstract: A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.

Abstract: The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by the delayed jitter signal.

Abstract: A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.