Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.

Abstract: A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.

Abstract: A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.

Abstract: A current-integrating amplifier is provided. The current-integrating amplifier comprises a pair of input voltage nodes having a voltage difference there between; A pair of current sources that generate a current that produces a voltage drop over a resistor that corresponds to an equivalent voltage difference between the pair of input voltage nodes; a pair of output voltage nodes; a pair of pMOSFETs connected to the pair of output voltage nodes; a first pair of nMOSFETs connected the pair of output voltage nodes, the pair of pMOSFETS, the pair of input voltage nodes, a resistor, and a second pair of nMOSFETS; a resistor connected to the pair of current sources; a second pair of nMOSFETs connected to the first and third pairs of nMOSFETs; and a third pair of nMOSFETs connected to the second pair of nMOSFETs and connected to a bias generator that provides a predetermined constant current.

Abstract: A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.

Abstract: According to one embodiment of the present invention an analog to digital converter comprises a track and hold unit, a plurality of current-integrating voltage shifters connected to the track and hold unit, a plurality of latches connected to the plurality of current-integrating voltage shifters, wherein a voltage offset of each latch in the plurality of latches is adjustable, wherein each current-integrating voltage shifter in the plurality of current-integrating voltage shifters drives a latch of the plurality of latches, wherein each current-integrating voltage shifter in the plurality of current-integrating voltage shifters corresponds to a voltage range, and wherein each latch connected to a current-integrating voltage shifter corresponds to a portion of the voltage range of the current-integrating voltage shifter.

Abstract: An integrated circuit for a memory input/output (I/O) pin has five different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. A T-coil circuit equalizes the capacitive loading of the high-speed functions. An exemplary embodiment provides a memory chip containing a multi-functional physical I/O circuit that can act as power or ground; as a DDR2 or DDR3 interface; as a high-speed differential receiver; or as a high-speed differential transmitter.

Abstract: A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.

Abstract: A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.

Abstract: The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by means of the delayed jitter signal.

Abstract: The present invention provides integrated line drivers useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of electrostatic discharge devices and process tolerances are minimized too. An example of an integrated line driver according to the invention comprises a first driver stage followed by a second driver stage, and a feedback unit forming with the second driver stage a control loop. The integrated line drivers are useable for driving data signals with high data rates wherein the area consumption of the line driver is minimized and wherein the influence of ESD devices and process tolerances are minimized. Advantageously, the integrated line driver according to the invention complies with chip design methodologies, where 10 or more routing metal layers are used.

Abstract: A self aligning trailer hitch, used by a driver alone without creating any personal lifting force, to couple and decouple a towing vehicle and a trailer, has a multiple piece assembly of a socket for securement to a towing vehicle, having a rotatable claw, which has a spherical recessed surface adapted to receive a portion of a lower ball of a vertical dual ball assembly, which is secured to a towed vehicle. Upon hitching the vehicles together, the rotatable claw contacts the lower ball, when this socket is moving horizontally, during movement of a towing vehicle toward the towed vehicle, causing the lower ball to be repositioned upwardly and over center, while being guided in a vertical plane, and then held in the radially upwardly repositioned spherical recessed surface of the rotatable claw. A three dimensional ramp guides the lower ball to fully contact the spherical recessed surface of the rotatable claw.