Abstract: In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.

Abstract: By significantly suppressing or eliminating the channeling effects during implantation of a dopant species into the semiconductor region, the contribution of energy contamination may be studied and the corresponding results may be used in selecting appropriate tool settings for an actual implantation process. In this way, the vertical dopant profile may be controlled more precisely than in conventional processes. In one particular embodiment, the channeling effect is suppressed by an appropriately performed amorphization implantation process.

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Abstract: An array of high aspect openings enables fast and accurate measurement of incidence angle deviation and/or beam divergence. The high aspect ratio assures that only ions of a predefined small incidence angle range may reach a conductive detection surface, thereby allowing efficient control of the ion beam parallelism by maximizing the beam current through the high aspect ratio openings. Moreover, if the array of openings is provided with individual beam current measurement points, spatially resolved intensity measurements may be performed that allow estimation of the beam shape. Thus, a movable Faraday cup assembly may be replaced with the stationary array of high aspect ratio openings, thereby improving tool reliability.

Abstract: The present invention provides an improved Faraday cup configuration that allows determination of a non-zero angle of incidence and/or a beam divergence with high accuracy. Moreover, by substantially simultaneously and continuously displaying information of a plurality of Faraday cups, the set-up of an implantation tool may be significantly facilitated and may be carried out in a substantially automated manner.

Abstract: An array of high aspect openings enables fast and accurate measurement of incidence angle deviation and/or beam divergence. The high aspect ratio assures that only ions of a predefined small incidence angle range may reach a conductive detection surface, thereby allowing efficient control of the ion beam parallelism by maximizing the beam current through the high aspect ratio openings. Moreover, if the array of openings is provided with individual beam current measurement points, spatially resolved intensity measurements may be performed that allow estimation of the beam shape. Thus, a movable Faraday cup assembly may be replaced with the stationary array of high aspect ratio openings, thereby improving tool reliability.

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

Abstract: When changing a dopant species in an implantation tool, typically a clean process is performed to reduce cross-contamination, which is considered a major issue in implant cycles applied in advanced CMOS processes. Especially, the employment of an implanter previously used for heavy ions may generate increased cross-contamination when subsequently used for boron or phosphorus implants at moderate energies. A clean implant process using xenon gas may effectively reduce this cross-contamination at shorter process times compared to a conventional argon clean step.

Abstract: In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.

Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

Abstract: Test wafer consumption is a significant contributor to overall cost of manufacturing in semiconductor industry due to scrapping the test wafers after one monitoring of implantation parameters. This invention provides a method to reuse the same test wafer for monitoring the implantation parameters more than once. This method comprises the possibility of implanting the same implant species together with identical implanting and annealing conditions as well as of implanting a broad variety of implant species together with varying implanting and annealing conditions. Therefore, this invention helps to significantly reduce the number of test wafers consumed in the implant-area.

Abstract: Liquid herbicidal composition, containing a grass herbicide that is suspended or dissolved in a non-aqueous liquid phase, a herbicide of the sulfonylurea type that is suspended in a non-aqueous liquid phase, and at least one surface-active substance.

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Abstract: A method of forming an oxide layer on a substrate comprises deposition of a mask layer with an opening for defining the area where the oxide layer is to be formed, and an ion implantation step performed with a tilt angle so as to obtain a varying ion concentration. In a subsequent single oxidation step, an oxide layer is formed having a thickness that varies in conformity with the ion concentration. This method may advantageously be applied to the formation of a gate insulation layer in a field effect transistor.

Abstract: A method of monitoring the temperature of a rapid thermal annealing (RTA) process and a test wafer for use in this process are disclosed. The method includes the step of forming a distorted surface region in a crystalline semiconductor wafer and the mounting of the wafer in a process chamber for performing the RTA process in a reaction gas containing ambient. The distorted surface region of the semiconductor wafer enables higher diffusion rates of reaction gas components into the wafer surface and therefore a higher growth rate of a reaction product film. The increase of the reaction product film thickness enables an increase of the film thickness measurement accuracy and thus the accuracy in determining the RTA temperature homogeneity. In one embodiment, a distorted surface region in a crystalline silicon test wafer is produced by implanting ions at low doses into a wafer substrate up to a pre-amorphization level of the surface crystalline lattice.

Abstract: Agrochemical granulated material which is dispersible in water and contains a mixture that is liquid, gel-like, or waxy at +25° C., comprising at least one agrochemical active ingredient and at least one surface-active compound and a thickening agent, and optionally having an outer coating, characterized in that the granulated material has plastic behavior at +25° C.