Patents by Inventor Christian N. Mohr
Christian N. Mohr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984189Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.Type: GrantFiled: March 18, 2021Date of Patent: May 14, 2024Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, John E. Riley
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Patent number: 11842985Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.Type: GrantFiled: October 13, 2022Date of Patent: December 12, 2023Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Scott E. Smith
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Patent number: 11810641Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.Type: GrantFiled: July 10, 2020Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Jennifer E. Taylor, Vijayakrishna J. Vankayala
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Patent number: 11710534Abstract: Embodiments presented herein are directed to testing and/or debugging a memory device of a memory module (e.g., a dual in-line memory module (DIMM)) without having to remove the DIMM from a corresponding computing device and without having to interrupt operation of the computing device. A particular memory device (e.g., DRAM) may be identified for testing and/or debugging based on a failure message. However, the failure message may not identify a specific location or hardware of the module that caused the failure. Embodiments presented herein provide techniques to obtain data for analysis to determine and/or deliver a cause of the failure while reducing or eliminating downtime of the computing device. Test modes to do so may include a synchronous test mode, an asynchronous test mode, and an analog compare mode. A test mode may be selected based on the failure or a signal/function of the DRAM to be tested or debugged.Type: GrantFiled: February 28, 2022Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Scott E. Smith, Manoj Vijay
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Publication number: 20230037349Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.Type: ApplicationFiled: October 13, 2022Publication date: February 9, 2023Inventors: Christian N. Mohr, Scott E. Smith
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Patent number: 11495577Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.Type: GrantFiled: June 5, 2020Date of Patent: November 8, 2022Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Scott E. Smith
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Patent number: 11437116Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: GrantFiled: April 17, 2020Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
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Publication number: 20210210122Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.Type: ApplicationFiled: March 18, 2021Publication date: July 8, 2021Inventors: Christian N. Mohr, John E. Riley
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Patent number: 10957364Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.Type: GrantFiled: September 26, 2018Date of Patent: March 23, 2021Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, John E. Riley
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Publication number: 20200342922Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.Type: ApplicationFiled: July 10, 2020Publication date: October 29, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Christian N. Mohr, Jennifer E. Taylor, Vijayakrishna J. Vankayala
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Publication number: 20200303349Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.Type: ApplicationFiled: June 5, 2020Publication date: September 24, 2020Inventors: Christian N. Mohr, Scott E. Smith
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Publication number: 20200243155Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: ApplicationFiled: April 17, 2020Publication date: July 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
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Patent number: 10714156Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.Type: GrantFiled: September 4, 2018Date of Patent: July 14, 2020Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Jennifer E. Taylor, Vijayakrishna J. Vankayala
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Patent number: 10692841Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.Type: GrantFiled: June 27, 2018Date of Patent: June 23, 2020Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Scott E. Smith
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Patent number: 10643734Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: GrantFiled: June 27, 2018Date of Patent: May 5, 2020Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
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Publication number: 20200098398Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Christian N. Mohr, John E. Riley
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Publication number: 20200075067Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.Type: ApplicationFiled: September 4, 2018Publication date: March 5, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Christian N. Mohr, Jennifer E. Taylor, Vijayakrishna J. Vankayala
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Publication number: 20200005885Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Applicant: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
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Publication number: 20200006291Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Inventors: Christian N. Mohr, Scott E. Smith
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Publication number: 20190348138Abstract: In a particular embodiment, a method of operating a memory device includes assigning a plurality of signals to a group and multiplexing the group of assigned signals onto a data transmission line. Each of the multiplexed signals can be individually demultiplexed by locally latching individual signals at corresponding target destinations. Demultiplexing each of the signals can be based on a phase signal received at the target destination and that includes the group which the corresponding individual signal was assigned to.Type: ApplicationFiled: May 11, 2018Publication date: November 14, 2019Inventors: Christian N. Mohr, Scott E. Smith