Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.

Abstract: A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.

Abstract: A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes a plurality of redundancy comparison circuitry coupled to a respective programmable element block storing addresses that are mapped to redundant memory of a memory plane. The redundancy address decoder further includes redundancy driver select logic coupled to each of the redundancy comparison circuitry to activate a selected one of the redundancy comparison circuitry for comparing a portion of a memory address corresponding to a memory location with the programmed addresses of the respective programmable element blocks, which leads to power reduction for column accesses to the memory device. The selection of the redundancy driver is based on the memory bank in which the memory location is located.

Abstract: Circuitry is provided to allow early switching of input signals from a first configuration directed to blow a first anti-fuse to a second configuration directed to blow a second anti-fuse, yet still allow complete blowing of the first anti-fuse. Such circuitry may be applied to methods of repairing a memory device after testing. Data concerning available repair cells may be stored in at least one on-chip redundancy register.

Abstract: A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes a plurality of redundancy comparison circuitry coupled to a respective programmable element block storing addresses that are mapped to redundant memory of a memory plane. The redundancy address decoder further includes redundancy driver select logic coupled to each of the redundancy comparison circuitry to activate a selected one of the redundancy comparison circuitry for comparing a portion of a memory address corresponding to a memory location with the programmed addresses of the respective programmable element blocks, which leads to power reduction for column accesses to the memory device. The selection of the redundancy driver is based on the memory bank in which the memory location is located.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: A preferred exemplary embodiment of the current invention concerns memory testing and repair processes, wherein circuitry is provided to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip address register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the address register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Data concerning available redundant cells may be stored in at least one on-chip redundancy register.

Abstract: A preferred exemplary embodiment of the current invention concerns a memory testing process, wherein circuitry is provided to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip address register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the address register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Data concerning available redundant cells may be stored in at least one on-chip redundancy register.