Abstract: Systems and methods for antenna impedance matching provide an integrated circuit (IC) configured to be placed proximate an antenna that includes a sensor based on a coupler having forward and reverse power detectors for detecting an impedance at the antenna and provides dynamic impedance matching. Further, exemplary aspects of the present disclosure contemplate using a single wire bus capable of supplying power and providing a bidirectional serial communication link to allow communication between the IC of the present disclosure and a control circuit (e.g., a bridge or transceiver). Further aspects of the present disclosure contemplate providing systems and methods for calibrating the IC at production. Further, the accuracy of the impedance sensor may be dependent on accurate determination of power and phase difference between forward and reverse coupled signals, and a system for removing an offset between the forward and reverse power detectors is disclosed.

Abstract: Systems and methods for antenna impedance matching provide an integrated. circuit (IC) configured to be placed proximate an antenna that includes a sensor based on a coupler having forward and reverse power detectors for detecting an impedance at the antenna and provides dynamic impedance matching. Further, exemplary aspects of the present disclosure contemplate using a single wire bus capable of supplying power and providing a bidirectional serial communication link to allow communication between the IC of the present disclosure and a control circuit (e.g., a bridge or transceiver). Further aspects of the present disclosure contemplate providing systems and methods for calibrating the IC at production. Further, the accuracy of the impedance sensor may be dependent on accurate determination of power and phase difference between forward and. reverse coupled signals, and a system for removing an offset between the forward and reverse power detectors is disclosed.

Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

Abstract: An overvoltage detector for an RF switch is disclosed. The overvoltage detector is made up of circuitry having a detector output that couples to a controller, a body voltage input that couples to a charge pump, and a body voltage output that couples to a body terminal of the RF switch. The overvoltage detector is configured to detect an overvoltage across the RF switch by monitoring body leakage current flowing between the body voltage input and the body voltage output. Upon detecting body leakage current over a predetermined level, the overvoltage detector generates an overvoltage signal at the detector output to indicate an overvoltage across the RF switch.

Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

Abstract: An RF phase offset detection system, which includes a first RF phase detector and a second RF phase detector, and measures a first phase offset between a first RF signal and a second RF signal, is disclosed. Each of the first RF signal and the second RF signal has a common RF frequency. The first RF phase detector detects and filters the first RF signal and the second RF signal to provide a first detection signal. The second RF phase detector receives and phase-shifts the second RF signal to provide a phase-shifted RF signal. The second RF phase detector further detects and filters the first RF signal and the phase-shifted RF signal to provide a second detection signal, such that a combination of the first detection signal and the second detection signal is representative of the first phase offset.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, a first decoupling path and a second decoupling path are provided for the first FET device and the last FET device in the FET device stack. Both decoupling paths are configured to pass a time-variant input signal during the open state. The first decoupling path may be coupled from the drain contact of the first FET device to the gate contact or the source contact. The second decoupling path may be coupled from the source contact of the last FET device to the gate contact or drain contact. The time-variant input signal bypasses the FET device stack through the first and second decoupling paths during the open state.

Abstract: Antenna tuning circuitry includes an antenna tuning node, an antenna tuning switch, and a resonant tuning circuit. The antenna tuning node is coupled to a resonant conduction element of an antenna. The antenna tuning switch and the resonant tuning circuit are coupled in series between the antenna tuning switch and the antenna tuning node, such that the resonant tuning circuit is between the antenna tuning node and the antenna tuning switch. The resonant tuning circuit is configured to resonate at one or more harmonic frequencies generated by the antenna tuning switch such that a high impedance path is formed between the antenna tuning switch and the antenna tuning node at harmonic frequencies generated by the antenna tuning switch. Accordingly, harmonic interference generated by the antenna tuning switch is prevented from reaching the antenna, while simultaneously allowing for tuning of the antenna.

Abstract: An RF phase offset detection system, which includes a first RF phase detector and a second RF phase detector, and measures a first phase offset between a first RF signal and a second RF signal, is disclosed. Each of the first RF signal and the second RF signal has a common RF frequency. The first RF phase detector detects and filters the first RF signal and the second RF signal to provide a first detection signal. The second RF phase detector receives and phase-shifts the second RF signal to provide a phase-shifted RF signal. The second RF phase detector further detects and filters the first RF signal and the phase-shifted RF signal to provide a second detection signal, such that a combination of the first detection signal and the second detection signal is representative of the first phase offset.

Abstract: An overvoltage detector for an RF switch is disclosed. The overvoltage detector is made up of circuitry having a detector output that couples to a controller, a body voltage input that couples to a charge pump, and a body voltage output that couples to a body terminal of the RF switch. The overvoltage detector is configured to detect an overvoltage across the RF switch by monitoring body leakage current flowing between the body voltage input and the body voltage output. Upon detecting body leakage current over a predetermined level, the overvoltage detector generates an overvoltage signal at the detector output to indicate an overvoltage across the RF switch.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, one or more decoupling paths are provided and are configured to pass the time-variant input signal during the open state of the FET device stack. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The decoupling paths may be connected so that the time-variant input signal bypasses a portion of the FET device stack during the open state.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, one or more decoupling paths are provided and are configured to pass the time-variant input signal during the open state of the FET device stack. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The decoupling paths may be connected so that the time-variant input signal bypasses a portion of the FET device stack during the open state.

Abstract: Antenna tuning switch circuitry includes an input port, a shunt switch, control circuitry, and an integrated ground. The shunt switch is coupled between the input port and the integrated ground. The control circuitry includes a control signal input port, a switch driver output port coupled to the shunt switch, and a ground connection port coupled to the integrated ground. The shunt switches, the RF input ports, the control circuitry, and the integrated ground are monolithically integrated on a single semiconductor die. The antenna tuning switch circuitry is adapted to selectively couple the input port to the integrated ground in order to alter one or more operating parameters of an attached antenna. By monolithically integrating the shunt switch together with the control circuitry and the integrated ground, the ON state impedance and the parasitic OFF state impedance of the antenna tuning switch circuitry can be significantly improved.

Abstract: An apparatus, which includes a first electronic device, a first nonlinear capacitance compensation circuit, and a capacitance compensation control circuit, is disclosed. The first electronic device has a first nonlinear capacitance and is coupled to the first nonlinear capacitance compensation circuit, which has a first compensation capacitance and receives a first compensation control signal. The capacitance compensation control circuit adjusts the first compensation capacitance using the first compensation control signal to at least partially linearize the first nonlinear capacitance.

Abstract: Switchable capacitive elements are disclosed, along with programmable capacitor arrays (PCAs). One embodiment of the switchable capacitive element includes a field effect transistor (FET) device stack, a first capacitor, and a second capacitor. The FET device stack is operable in an open state and in a closed state and has a plurality of FET devices coupled in series to form the FET device stack. The first capacitor and the second capacitor are both coupled in series with the FET device stack. However, the first capacitor is coupled to a first end of the FET device stack while the second capacitor is coupled to a second end opposite the first end of the FET device stack. In this manner, the switchable capacitive element can be operated without a negative charge pump, with decreased bias swings, and with a better power performance.

Abstract: Switching circuitry is provided for a mobile terminal having a Time Division Multiple Access (TDMA) mode of operation and a Frequency Division Duplex (FDD) mode of operation. The switching circuitry includes resonant tank circuitry having a controllable resonant frequency and an output coupled to an antenna of the mobile terminal. The switching circuitry also includes a transmit switch that couples TDMA transmit circuitry to an input of the resonant tank circuitry when transmitting in the TDMA mode of operation, a receive switch that couples TDMA receive circuitry to the input of the resonant tank circuitry when receiving in the TDMA mode of operation, and a FDD switch that couples a FDD transceiver to the output of the resonant tank circuitry when in the FDD mode of operation. The controllable resonant frequency is controlled such that the transmit and receive switches are isolated from the antenna during FDD operation.

Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

Abstract: The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.

Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. A control circuit provides biasing voltages to the gate, source, and drain contacts of each of the plurality of FET devices to switch the FET device stack to and from a closed state and an open state. In the open state, the gate contacts of each of the plurality of FET devices are biased by the control circuit at the second voltage. To prevent activation in the open state, the control circuit biases the drain contacts and source contacts of each of the plurality of FET devices at the first voltage. The first voltage is positive relative to a reference voltage, such as ground, while the second voltage is non-negative relative to the reference voltage but less than the first voltage.