Abstract: Antenna tuning circuitry includes an antenna tuning node, an antenna tuning switch, and a resonant tuning circuit. The antenna tuning node is coupled to a resonant conduction element of an antenna. The antenna tuning switch and the resonant tuning circuit are coupled in series between the antenna tuning switch and the antenna tuning node, such that the resonant tuning circuit is between the antenna tuning node and the antenna tuning switch. The resonant tuning circuit is configured to resonate at one or more harmonic frequencies generated by the antenna tuning switch such that a high impedance path is formed between the antenna tuning switch and the antenna tuning node at harmonic frequencies generated by the antenna tuning switch. Accordingly, harmonic interference generated by the antenna tuning switch is prevented from reaching the antenna, while simultaneously allowing for tuning of the antenna.

Abstract: An apparatus, which includes a first electronic device, a first nonlinear capacitance compensation circuit, and a capacitance compensation control circuit, is disclosed. The first electronic device has a first nonlinear capacitance and is coupled to the first nonlinear capacitance compensation circuit, which has a first compensation capacitance and receives a first compensation control signal. The capacitance compensation control circuit adjusts the first compensation capacitance using the first compensation control signal to at least partially linearize the first nonlinear capacitance.

Abstract: The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element.

Abstract: Antenna tuning switch circuitry includes an input port, a shunt switch, control circuitry, and an integrated ground. The shunt switch is coupled between the input port and the integrated ground. The control circuitry includes a control signal input port, a switch driver output port coupled to the shunt switch, and a ground connection port coupled to the integrated ground. The shunt switches, the RF input ports, the control circuitry, and the integrated ground are monolithically integrated on a single semiconductor die. The antenna tuning switch circuitry is adapted to selectively couple the input port to the integrated ground in order to alter one or more operating parameters of an attached antenna. By monolithically integrating the shunt switch together with the control circuitry and the integrated ground, the ON state impedance and the parasitic OFF state impedance of the antenna tuning switch circuitry can be significantly improved.

Abstract: The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element.

Abstract: A radio frequency (RF) switch die which includes an antenna port, a plurality of RF ports, a switch fabric for selectively coupling one or more of the RF ports to the antenna port, and control circuitry that is adapted to, in a first mode, direct the switch fabric to couple any one of the plurality of RF ports individually to the antenna port, and in a second mode, couple a selected group of the RF ports to the antenna port. The RF switch die may include M number of RF ports, and be relatively easily reconfigured to provide N number of RF ports, wherein N is less than M. Groups of RF ports may be coupled together to form coupled RF ports that offer different electrical characteristics than non-coupled RF ports.

Abstract: Adjustable impedance tuning circuitry includes a first impedance matching terminal, a second impedance matching terminal, and a plurality of passive components adapted to match the impedance of the first impedance matching terminal and the second impedance matching terminal. The plurality of passive components includes one or more tunable components adapted to adjust the impedance of the adjustable impedance tuning circuitry to maintain an impedance match between the first impedance matching terminal and the second impedance matching terminal over a variety of operating conditions. Each of the one or more tunable components includes one or more switches adapted to selectively alter the impedance of the tunable component. The one or more switches are integrated onto a single semiconductor die in order to facilitate the performance of the adjustable impedance tuning circuitry over a wide bandwidth.

Abstract: Switchable capacitive elements are disclosed, along with programmable capacitor arrays (PCAs). One embodiment of the switchable capacitive element includes a field effect transistor (FET) device stack, a first capacitor, and a second capacitor. The FET device stack is operable in an open state and in a closed state and has a plurality of FET devices coupled in series to form the FET device stack. The first capacitor and the second capacitor are both coupled in series with the FET device stack. However, the first capacitor is coupled to a first end of the FET device stack while the second capacitor is coupled to a second end opposite the first end of the FET device stack. In this manner, the switchable capacitive element can be operated without a negative charge pump, with decreased bias swings, and with a better power performance.

Abstract: A radio frequency (RF) switch die which includes an antenna port, a plurality of RF ports, a switch fabric for selectively coupling one or more of the RF ports to the antenna port, and control circuitry that is adapted to, in a first mode, direct the switch fabric to couple any one of the plurality of RF ports individually to the antenna port, and in a second mode, couple a selected group of the RF ports to the antenna port. The RF switch die may include M number of RF ports, and be relatively easily reconfigured to provide N number of RF ports, wherein N is less than M. Groups of RF ports may be coupled together to form coupled RF ports that offer different electrical characteristics than non-coupled RF ports.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. A control circuit provides biasing voltages to the gate, source, and drain contacts of each of the plurality of FET devices to switch the FET device stack to and from a closed state and an open state. In the open state, the gate contacts of each of the plurality of FET devices are biased by the control circuit at the second voltage. To prevent activation in the open state, the control circuit biases the drain contacts and source contacts of each of the plurality of FET devices at the first voltage. The first voltage is positive relative to a reference voltage, such as ground, while the second voltage is non-negative relative to the reference voltage but less than the first voltage.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, one or more decoupling paths are provided and are configured to pass the time-variant input signal during the open state of the FET device stack. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The decoupling paths may be connected so that the time-variant input signal bypasses a portion of the FET device stack during the open state.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, a first decoupling path and a second decoupling path are provided for the first FET device and the last FET device in the FET device stack. Both decoupling paths are configured to pass a time-variant input signal during the open state. The first decoupling path may be coupled from the drain contact of the first FET device to the gate contact or the source contact. The second decoupling path may be coupled from the source contact of the last FET device to the gate contact or drain contact. The time-variant input signal bypasses the FET device stack through the first and second decoupling paths during the open state.

Abstract: The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.

Abstract: The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance and a drain-to-gate resistance of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element, a resistive element, a source-coupled level shifting diode, and a reverse protection diode. Therefore, the ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

Abstract: The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

Abstract: The present invention includes a silicon-on-insulator (SOI) wafer that enhances certain performance parameters by increasing silicon device layer and insulator layer thicknesses and increasing silicon handle wafer resistivity. By increasing the silicon device layer thickness, effects of the floating body problem may be significantly reduced. By increasing the insulator layer thickness and the silicon handle wafer resistivity, influences from the silicon handle wafer on devices formed using the silicon device layer may be significantly reduced. As a result, standard tools, methods, and processes may be used.

Abstract: Methods and apparatus for ESD protection of pseudomorphic high electron mobility transistor (pHEMT) circuitry are described. In one method, an ESD surge is detected at a trigger circuit. An ESD protection circuit is triggered. Current flow within the trigger circuit is limited and ESD energy is dispersed to a ground plane via the ESD protection circuit.

Abstract: The present invention is a wide dynamic range antenna switch that, when disabled, has a stable input impedance over a wide power range. The wide dynamic range antenna switch includes multiple transistors, which are coupled in series, to provide a main signal path between an antenna connection and a radio connection. Direct current (DC) bias signals are provided to each of the transistors to ensure than when the antenna switch is disabled, the input impedance is stable. A control input, which may operate with low voltage control signals, enables or disables the antenna switch. The antenna switch may be coupled with other antenna switches in a communications system with multiple transceivers sharing a common antenna, and with a wide range of transmitter output power levels. Different embodiments of the present invention provide different DC bias circuit architectures.