Abstract: The combination valve comprises a tubular center part, a gas inlet which is arranged on the outer shell of the tubular center part, a gas outlet A which is arranged adjacent to the gas inlet on the outer shell of the tubular center part, a first branch which is arranged opposite the gas outlet on the outer shell of the tubular center part, and a second branch which is arranged opposite the gas inlet on the outer shell of the tubular center part. The first branch is connected to the second branch via a cooler. A rotary slide is mounted centrally in the tubular center part such that it can rotate about the longitudinal axis of the tubular centre part. Depending on the operating state, the rotary slide shuts off at least partially the gas inlet, the gas outlet, the first branch and the second branch.

Abstract: The combination valve comprises a tubular center part, a gas inlet which is arranged on the outer shell of the tubular center part, a gas outlet A which is arranged adjacent to the gas inlet on the outer shell of the tubular center part, a first branch which is arranged opposite the gas outlet on the outer shell of the tubular center part, and a second branch which is arranged opposite the gas inlet on the outer shell of the tubular center part. The first branch is connected to the second branch via a cooler. A rotary slide is mounted centrally in the tubular center part such that it can rotate about the longitudinal axis of the tubular centre part. Depending on the operating state, the rotary slide shuts off at least partially the gas inlet, the gas outlet, the first branch and the second branch.

Abstract: Methods and apparatus for setting various terminations of a memory chip. The memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.

Abstract: A memory device includes at least two DRAM memory modules, at least one external ECC module, and a memory controller. The external ECC module provides the memory modules with ECC functionality. Each memory module is connected to the memory controller via a respective memory channel. The external ECC modules are connected to the memory controller via a common ECC channel. Each external ECC module is assigned to a group of the memory modules. The memory modules of one group with respective ECC modules are synchronously operated by the memory controller.

Abstract: A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals for controlling the respective delay devices are provided by synchronization latches, which receive a clock obtained by the output signal of the first delay device for obtaining the fine setting. The delay locked loop enables a linear operating behavior at a high operating frequency and is particularly suitable when a differential embodiment of the two delay devices is used.

Abstract: A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit.

Abstract: A device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.

Abstract: The present invention is electronically driven locking device for a locking element of a motor vehicle. The device has a motor, a gear wheel including a gear ring, a hub, and an elastic intermediate element, and a control disk. The motor is linked to the gear ring via a worm gear which is arranged to turn the gear. The control disk is linked to the locking element such that when the gear ring is turned, the hub is turned via the intermediate element which in turn engages the locking element to close or open. The intermediate element is arranged to absorb kinetic energy in the device.

Abstract: The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

Abstract: Methods and apparatus for setting various terminations of a memory chip. In one embodiment, the memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.

Abstract: A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit.

Abstract: The invention relates to a device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.

Abstract: Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.

Abstract: The present invention relates to an accelerator pedal for a motor vehicle, especially one with an automatic gearbox. The pedal includes a pedal arm which in one end area thereof is pivotally mounted about a pivoting axis and which in the other end thereof is provided with a pedal plate which can be impinged upon the force by the driver. When force is exerted upon the pedal plate, the pedal arm can be pivoted into an absolute final position when a kick down switch is actuated, wherein a signal can be produced by the kick down switch and can be fed to a control electronics system. The kick down switch comprises a permanent magnet, the magnet force thereof being used to retain a magnetically conducting component on a magnetic return element whereby the component can be moved away from the magnetic return element as a result of the movement of the pedal arm into an end position.

Abstract: The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

Abstract: An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

Abstract: An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

Abstract: Treatment of a skin disease selected from acne, rosacea, atopical dermatitis, and various ulcers, by topically applying a suitable pharmaceutical composition containing an effective amount of taurolidine, taurultam or a mixture containing both.

Abstract: The present invention relates to an accelerator pedal for a motor vehicle, especially one with an automatic gearbox. The pedal includes a pedal arm which in one end area thereof is pivotally mounted about a pivoting axis and which in the other end thereof is provided with a pedal plate which can be impinged upon the force by the driver. When force is exerted upon the pedal plate, the pedal arm can be pivoted into an absolute final position when a kick down switch is actuated, wherein a signal can be produced by the kick down switch and can be fed to a control electronics system. The kick down switch comprises a permanent magnet, the magnet force thereof being used to retain a magnetically conducting component on a magnetic return element whereby the component can be moved away from the magnetic return element as a result of the movement of the pedal arm into an end position.

Abstract: The present invention relates to a drive device having an actuating drive for driving a displaceable element, in particular a closing device of a motor vehicle door, by means of a gear wheel that has a ring gear and a hub. The ring gear of the gear wheel can be indirectly or directly driven by the actuating drive and the displaceable element can be impinged indirectly or directly by the hub of the gear wheel. The aid of the invention is to provide a drive device that has particularly small space requirements, which at the same time allows the kinetic energy of the actuating device to be reliably intercepted. To achieve this, the ring gear of the gear wheel and the hub of the gear wheel include a predominantly inflexible material and are interconnected by means of an elastic intermediate element.