Abstract: Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.

Abstract: Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

Abstract: The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

Abstract: Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.

Abstract: An integrated circuit contains a register circuit for storing reference data for a test operation of the integrated circuit and a comparison circuit for comparing data to be read out. The comparison circuit outputs a plurality of comparison signals representing compressed comparison results. A plurality of output circuits are connected to the output of the comparison circuit, the output circuits receive one of the comparison signals in each case. The comparison signals are present at the output circuit over a plurality of clock edges or clock periods of a control clock. Each of the output circuits is connected to an interface pad for externally outputting the comparison signals. In the test operation, an external test device is connected to the interface pads of the integrated circuit. Despite a reduction in the transmission frequency to the test device, the full information content of the comparison signals can be transmitted.

Abstract: An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

Abstract: An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

Abstract: A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals for controlling the respective delay devices are provided by synchronization latches, which receive a clock obtained by the output signal of the first delay device for obtaining the fine setting. The delay locked loop enables a linear operating behavior at a high operating frequency and is particularly suitable when a differential embodiment of the two delay devices is used.

Abstract: The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

Abstract: An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.

Abstract: The module (10) serves for producing a force hysteresis during pivoting of a rotary element (14, 16) which is mounted rotatably in a housing (12) and on which there is secured at least one spring element (20), of which the free end slides, via a friction element (18), on a stationary friction surface (22). In order for it not to be necessary to rely on separate restoring mechanisms, it is proposed that, in all the angled positions of the rotary element (14, 16) relative to the housing (12), the reaction force of the spring element (22) subjects the rotary element (14, 16) to a restoring moment about the rotary spindle (24). Such a module (10), with a compact construction, makes it possible, with the aid of a spring element (20), to produce both the restoring forces and the frictional forces necessary for the hysteresis.

Abstract: A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

Abstract: The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

Abstract: An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.

Abstract: Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.

Abstract: A pedal (2), in particular for a motor vehicle, has a pedal arm (6) which can be deflected at its first end region (8) by a force (4), in particular a foot force, is mounted at its second end region (10) in a manner such that it can pivot about a pivot spindle (18) mounted in a housing (16), and is acted upon in a manner such that it can be pivoted back into an initial position by a restoring spring element (20) which surrounds the pivot spindle (18). In this arrangement, the restoring spring element (20) is supported on a first lever arm (36) of a pivotably mounted lever (38). The second lever arm (44) of the lever (38) bears via a friction body (50) against a friction surface (56). The friction surface (56) in turn can be pivoted about the pivot spindle (18) of the pedal arm (6) and is arranged on the second end region (10) of the pedal arm (6).

Abstract: Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

Abstract: The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

Abstract: A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

Abstract: The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.