Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

Abstract: An instruction cache includes instruction storage, a plurality of lock indicators, and control logic. The instruction storage includes a plurality of cache blocks to store instructions. Each of the lock indicators is associated with one of the cache blocks so as to control access to the associated cache block. The control logic is configured to: set to a write disable state, on access of a given one of the cache blocks, a given one of the lock indictors associated with the given one of the cache blocks; to determine whether a given instruction is stored in the instruction storage; and to deny write access to the given one of the cache blocks that is assigned to store the given instruction based on the given one of the block indicators being set to the write disable state.

Abstract: A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words.

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na?1 multiplied with the second operand bits 0 to nb?2, selectively inverting the single bit products of the signed second operand bits 0 to na?2 multiplied with the signed second operand bit nb?1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb?1, na?1 and na+nb?1 for receiving a final product.

Abstract: An apparatus and method system and method for increasing performance in a processor or other instruction execution device while minimizing energy consumption. A processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of a subset of the instructions executable via the first execution control unit.

Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the instruction pipeline.

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

Abstract: A processor includes an execution unit and a subroutine cache. The execution unit is configured to execute instructions. The subroutine cache us configured to provide instructions of a subroutine to the execution unit for execution. The subroutine cache includes subroutine instruction storage, a subroutine address register, and subroutine cache control logic. The subroutine control logic is configured to: identify a subroutine call instruction provided to the execution unit; determine whether an instruction of a subroutine invoked by the subroutine call instruction is stored in the subroutine instruction storage by evaluating a subroutine validity indicator that indicates whether at least a portion of the subroutine is stored in the subroutine instruction storage; and provide the instruction of the subroutine to the execution unit based on the subroutine validity indicator indicating that at least a portion of the subroutine is stored in the subroutine instruction storage.

Abstract: A method and apparatus for executing program loops. A processor, includes an execution unit and an instruction fetch buffer. The execution unit is configured to execute instructions. The instruction fetch buffer is configured to store instructions for execution by the execution unit. The instruction fetch buffer includes a loop buffer configured to store instructions of an instruction loop for repeated execution by the execution unit. The loop buffer includes buffer control logic. The buffer control logic includes pointers, and is configured to predecode a loop jump instruction, identify loop start and loop end instructions using the predecoded loop jump instruction and pointers; and to control non-sequential instruction execution of the instruction loop. The width of the pointers is determined by loop buffer length and is less than a width of an address bus for fetching the instructions stored in the loop buffer from an instruction memory.

Abstract: A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is configured to fetch instructions from memory into the instruction pre-fetch buffer. The instruction decode unit is coupled to the instruction pre-fetch buffer and upon decoding a call instruction from the instruction pre-fetch buffer, causes next N instruction words of the instruction pre-fetch buffer to be preserved for execution after completing execution of a software module indicated by the call instruction, and causes the instruction fetch unit to begin fetching instructions of the software module from the memory at an address indicated by the call instruction. Upon completion of execution of the software module, the instruction decode unit begins to decode the preserved N instruction words while the instruction fetch unit concurrently fetches instruction words from beginning at an address after the N instruction words.

Abstract: An independently timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier. The clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier. The clock generator uses circuit with identical logical design including the same standard cells, the same logic design or the same floor plan. Close matching of these circuit causes the multiplier and the clock generator to experience the same PVT speed variations.

Abstract: A system and method for controlling operation of a pipeline. In one embodiment, a pipelined datapath includes a plurality of processing stages and a pipeline controller. Each of the processing stages is configured to further processing provided by a previous one of the processing stages. The pipeline controller is configured to control operation of the processing stages. The pipeline controller includes a pipelined finite state machine. The pipelined finite state machine includes a plurality of control stages. Each of the control stages is configured to control operation of a single one of the processing stages, and to receive a state value that defines a state of the control stage for controlling the single one of the processing stages from a previous control stage.

Abstract: A system and method for reducing pipeline latency. In one embodiment, a processing system includes a processing pipeline. The processing pipeline includes a plurality of processing stages. Each stage is configured to further processing provided by a previous stage. A first of the stages is configured to perform a first function in a pipeline cycle. A second of the stages is disposed downstream of the first of the stages, and is configured to perform, in a pipeline cycle, a second function that is different from the first function. The first of the stages is further configured to selectably perform the first function and the second function in a pipeline cycle, and bypass the second of the stages.

Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na?1 multiplied with the second operand bits 0 to nb?2, selectively inverting the single bit products of the signed second operand bits 0 to na?2 multiplied with the signed second operand bit nb?1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb?1, na?1 and na+nb?1 for receiving a final product.