Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na-1 multiplied with the second operand bits 0 to nb-2, selectively inverting the single bit products of the signed second operand bits 0 to na-2 multiplied with the signed second operand bit nb-1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb-1, na-1 and na+nb-1 for receiving a final product.

Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

Abstract: A self-timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier. The clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier. The clock generator uses circuit with identical logical design including the same standard cells, the same logic design or the same floor plan. Close matching of these circuit causes the multiplier and the clock generator to experience the same PVT speed variations.

Abstract: A WLAN (Wireless Local Area Network) communication device for performing communication in a WLAN network is provided that comprises a physical connection unit, a physical connection oscillator, and a control unit. The physical connection unit is for providing a physical connection of the WLAN communication device to a wireless communication medium. The physical connection oscillator is for providing a physical connection clock signal to the physical connection unit. The control unit is for controlling operation of the physical connection oscillator. The WLAN communication device is operable in a communication mode and in a deep sleep mode. The control unit is adapted to deactivate the physical connection oscillator when the deep sleep mode is entered. Embodiments may provide an extended reduction of the power consumption of the WLAN communication device.

Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na-1 multiplied with the second operand bits 0 to nb-2, selectively inverting the single bit products of the signed second operand bits 0 to na-2 multiplied with the signed second operand bit nb-1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb-1, na-1 and na+nb-1 for receiving a final product.

Abstract: The present invention relates to a multiply apparatus and a method for multiplying a first operand consisting of na bits and a second operand consisting of nx bits. In one embodiment the multiply apparatus comprising a CSA (CSA) unit with nx rows each comprising na AND gates for calculating a single bit product of two single bit input values and adder cells for adding results of a preceding row to a following row and a last output row for outputting a carry vector and a sum vector, and logic circuitry for selectively inverting the single bit products at the most significant position of the nx?1 first rows and at the na?1 least significant positions of the output row in response to a first configuration signal before inputting the selectively inverted single bit products to respective adder cells for switching the CSA unit selectively between processing of signed two's complement operands and unsigned operands in response to the first configuration signal.

Abstract: A WLAN (Wireless Local Area Network) communication device including a first buffer, a second buffer and a shared backoff generator and corresponding methods and integrated circuit chips provided. The first buffer is for queuing first data packets to be transmitted by the WLAN communication device after a transmission channel has been idle for at least a first backoff time. The second buffer is for queuing second data packets to be transmitted by the WLAN communication device after the transmission channel has been idle for at least a second backoff time. The shared backoff generator is adapted to generate a first and a second backoff start value used to determine the first and second backoff times, respectively. Embodiments may reduce the hardware consumption and thus manufacturing and product costs.

Abstract: A WLAN (Wireless Local Area Network) communication device including a first buffer, a second buffer and a shared backoff generator and corresponding methods and integrated circuit chips provided. The first buffer is for queuing first data packets to be transmitted by the WLAN communication device after a transmission channel has been idle for at least a first backoff time. The second buffer is for queuing second data packets to be transmitted by the WLAN communication device after the transmission channel has been idle for at least a second backoff time. The shared backoff generator is adapted to generate a first and a second backoff start value used to determine the first and second backoff times, respectively. Embodiments may reduce the hardware consumption and thus manufacturing and product costs.

Abstract: A WLAN (Wireless Local Area Network) communication device for performing communication in a WLAN network is provided that comprises a physical connection unit, a physical connection oscillator, and a control unit. The physical connection unit is for providing a physical connection of the WLAN communication device to a wireless communication medium. The physical connection oscillator is for providing a physical connection clock signal to the physical connection unit. The control unit is for controlling operation of the physical connection oscillator. The WLAN communication device is operable in a communication mode and in a deep sleep mode. The control unit is adapted to deactivate the physical connection oscillator when the deep sleep mode is entered. Embodiments may provide an extended reduction of the power consumption of the WLAN communication device.