Abstract: Nickel silicide is formed on the basis of a gaseous precursor, such as nickel tetra carbonyl, wherein the equilibrium of the decomposition of this gas may be controlled to obtain a highly selective nickel silicide formation rate. Moreover, any etch step for removing excess nickel may be avoided, since only minute amounts of nickel may form on exposed surfaces, which may then be effectively removed by correspondingly shifting the equilibrium. Consequently, reduced process complexity, enhanced controllability and enhanced tool lifetime may be obtained.

Abstract: During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. The recess is filled with a material comprising silver.

Abstract: By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction.

Abstract: By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction.

Abstract: By incorporating an atomic species of increased covalent radius, which may at least partially substitute germanium, a highly efficient strain mechanism may be provided, in which the risk of stress relief due to germanium conglomeration and lattice defects may be reduced. The atomic species of increased radius, such as tin, may be readily incorporated by epitaxial growth techniques on the basis of tin hydride.

Abstract: By providing a highly stressed interlayer dielectric material, the performance of at least one type of transistor may be increased due to an enhanced strain-inducing mechanism. For instance, by providing a highly compressive silicon dioxide of approximately 400 Mega Pascal and more as an interlayer dielectric material, the drive current of the P-channel transistors may be increased by 2% and more while not unduly affecting the performance of the N-channel transistors.

Abstract: By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precursor solution, which may exhibit a substantially self-aligned and self-limiting deposition behavior.

Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.

Abstract: By reducing the effect of particle bombardment during the sequence for forming a metal silicide in semiconductor devices, the defect rate and the metal silicide uniformity may be enhanced. For this purpose, the metal may be deposited without an immediately preceding sputter etch process, wherein, in a particular embodiment, an additional oxidation process is performed to efficiently remove any silicon contaminations and surface impurities by a subsequent wet chemical treatment on the basis of HF, which is followed by the metal deposition.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. The recess is filled with a material comprising silver.

Abstract: By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precursor solution, which may exhibit a substantially self-aligned and self-limiting deposition behavior.

Abstract: By forming a cap layer on a dielectric barrier layer of a low-k dielectric material stack, the interaction of UV radiation during the generation of pores in the low-k dielectric material may be significantly reduced. In some illustrative embodiments, the cap layer may comprise titanium oxide and/or vanadium oxide which may provide a high degree of reflectivity and absorption, respectively. The layer thickness of the cap layer may be 10 nm or significantly less, thereby reducing any adverse influence on the overall performance of the resulting layer stack.

Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.

Abstract: By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction.

Abstract: By incorporating an atomic species of increased covalent radius, which may at least partially substitute germanium, a highly efficient strain mechanism may be provided, in which the risk of stress relief due to germanium conglomeration and lattice defects may be reduced. The atomic species of increased radius, such as tin, may be readily incorporated by epitaxial growth techniques on the basis of tin hydride.

Abstract: By reducing the effect of particle bombardment during the sequence for forming a metal silicide in semiconductor devices, the defect rate and the metal silicide uniformity may be enhanced. For this purpose, the metal may be deposited without an immediately preceding sputter etch process, wherein, in a particular embodiment, an additional oxidation process is performed to efficiently remove any silicon contaminations and surface impurities by a subsequent wet chemical treatment on the basis of HF, which is followed by the metal deposition.

Abstract: Nickel silicide is formed on the basis of a gaseous precursor, such as nickel tetra carbonyl, wherein the equilibrium of the decomposition of this gas may be controlled to obtain a highly selective nickel silicide formation rate. Moreover, any etch step for removing excess nickel may be avoided, since only minute amounts of nickel may form on exposed surfaces, which may then be effectively removed by correspondingly shifting the equilibrium. Consequently, reduced process complexity, enhanced controllability and enhanced tool lifetime may be obtained.

Abstract: A technique is disclosed which enables the formation of a metallization layer being substantially comprised of a low-k dielectric material, wherein a compressive stress layer provides enhanced electromigration behavior of the metallization layer. In particular embodiments, a compressive silicon dioxide layer may be formed on or in the vicinity of a dielectric barrier layer and a metallization layer based on SiCOH.

Abstract: By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.