Abstract: A low-k dielectric layer stack is provided including a silicon based dielectric material with a low permittivity, wherein an intermediate silicon oxide based etch indicator layer is arranged at a depth that represents the depth of a trench to be formed in the dielectric layer stack. A thickness of the etch indicator layer is sufficiently small to not unduly compromise the overall permittivity of the dielectric layer stack. On the other hand, the etch indicator layer provides a prominent optical emission spectrum to reliably determine the time point when the etch process has reached the etch indicator layer. Thus, the depth of trenches in highly sophisticated low-k dielectric layer stacks may reliably be adjusted to minimize resistance variations of the metal lines.

Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.

Abstract: During the formation of a metallization layer according to the “via first, trench last” sequence with a low-k dielectric layer, resist poisoning is significantly reduced in that a low-density oxide layer is formed on the low-k dielectric layer, for example by converting an upper portion thereof into an oxide so that prior to and during the formation of the cap layer, out-gassing of volatile materials is enhanced. Since the density of the cap layer is reduced compared to cap layers formed by conventional deposition techniques, out-gassing may still be maintained across the entire substrate surface during the via and trench formation so that a critical level of resist contamination may reliably be avoided.

Abstract: A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysilicon line sidewalls are no longer covered with spacer oxide but all silicide pre-cleans can clear the poly sidewalls completely which thus leads to improved silicidation conditions, resulting in gate lines exhibiting very low sheet resistivity.

Abstract: A method is provided for forming polysilicon line structures, such as gate electrodes of field effect transistors, according to which oxide spacers are removed from the sidewalls of the poly gate lines before depositing the liner oxide. Accordingly, after formation of the final spacers, the polysilicon line sidewalls are no longer covered with spacer oxide but all silicide pre-cleans can clear the poly sidewalls completely which thus leads to improved silicidation conditions, resulting in gate lines exhibiting very low sheet resistivity.

Abstract: A low-k dielectric layer stack is provided including a silicon based dielectric material with a low permittivity, wherein an intermediate silicon oxide based etch indicator layer is arranged at a depth that represents the depth of a trench to be formed in the dielectric layer stack. A thickness of the etch indicator layer is sufficiently small to not unduly compromise the overall permittivity of the dielectric layer stack. On the other hand, the etch indicator layer provides a prominent optical emission spectrum to reliably determine the time point when the etch process has reached the etch indicator layer. Thus, the depth of trenches in highly sophisticated low-k dielectric layer stacks may reliably be adjusted to minimize resistance variations of the metal lines.

Abstract: In a method of cleaning a deposition process chamber, a remotely generated activated gas is supplied to the process chamber, in which, depending on the type of excitation means used, a specified chamber pressure in combination with a two-step clean process allows one to significantly reduce nitrogen fluoride (NF3) consumption and increase throughput.

Abstract: This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films.

Abstract: A dielectric layer comprising a benzocyclobutene (BCB)-based low dielectric constant (low k) material is formed on a surface of a semiconductor wafer substrate by (a) spin coating a layer of a fluid material comprising BCB in a liquid solvent or dispersant vehicle on the substrate; (b) baking the coated substrate at a first temperature and for a first time interval to remove the solvent; (c) curing the baked coating by heating at a second temperature higher than the first temperature, and for a second time interval; and (d) subjecting the substrate with cured coating thereon to a cool-down treatment at a third temperature and for a third time interval. Embodiments include performing steps (a)-(d) consecutively and in the same apparatus. Other embodiments include processing in an "on track" type automated semiconductor processing apparatus.