Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract: The surfaces of wordline stacks and intermediate areas of a main substrate surface are covered with an oxynitride liner. Either sidewall spacers of BPSG are formed or a further liner of nitride is deposited and spacers of oxide are formed. These spacers are used in a peripheral area of addressing circuitry to implant doped source/drain regions. The oxynitride reduces the stress between the nitride and the semiconductor material and prevents charge carriers from penetrating out of a memory layer of nitride into the liner.

Abstract: A non-volatile semiconductor memory (30) comprising a semiconductor substrate (1) and a plurality of memory cells (19) and methods for manufacturing such a memory is provided. Each memory cell (19) comprises a charge-trapping element (5), a gate stack (20), nitride spacers (10) and electrically insulating elements (21). The charge-trapping element (5) is arranged on the semiconductor substrate (1) and comprises a nitride layer (3) sandwiched between a bottom oxide layer (2) and a top oxide layer (4), the charge-trapping element (5) having two lateral sidewalls (24) opposed to one another. The gate stack (20) is arranged on top of the charge-trappinig element (5), the gate stack having two lateral sidewalls (25) opposing one another. The electrically insulating elements (21) are disposed at opposing sidewalls (24) of the charge-trapping element (5) and cover the sidewalls (24) of the charge-trapping element (5).

Abstract: A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Abstract: In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

Abstract: In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations (7) that are widened for division into slices. Instead of this, the interconnects present below a bit line may be omitted or two mutually adjacent bit lines (41, 42) may be wired up in such a way that the memory transistors present between them operate only in the dummy mode.

Abstract: A semiconductor device is formed by forming a plurality of trenches in a semiconductor body. The trenches alternate between active trenches and isolation trenches with the isolation trenches being deeper than the active trenches. The semiconductor body is doped so that a top surface of the semiconductor body adjacent each active trench and a floor of each active trench is doped. Memory cell components are formed in each active trench. The memory cell components include a gate electrode and a charge-trapping layer disposed between the gate electrode and a sidewall of the trench. The charge-trapping layer includes a memory layer disposed between first and second limiting layers. Bitlines are formed over the semiconductor body and electrically coupled doped regions adjacent to the top surface of the semiconductor body adjacent the active trenches. Bitline contacts are coupled to the bitlines.

Abstract: Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.

Abstract: A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.

Abstract: Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.

Abstract: In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

Abstract: Isolation trench arrangement, which isolates adjacent semiconductor structures (1), (2), an isolation trench (3) being formed in such a way that it penetrates from a substrate surface into the substrate volume (0) and has at least one insulating substance (20) and at least one conductive substance (21), and the conductive substance (21) is electrically conductively connected to the substrate (0) via an electrically conductive connection (22).

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract: A method is provided for operating an electrical writable and erasable memory cell, which has a channel region (2) that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Abstract: A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.

Abstract: In a matrix-shaped configuration of memory transistors, word lines are disposed on a top side of a semiconductor body and are parallel to one another. Bit lines run transversely with respect thereto and are formed by polysilicon strips which are applied on the top side and are isolated from the semiconductor body by barrier layers functioning as diffusion barriers.

Abstract: In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (2), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer (16) is reached, and afterward a polysilicon layer (18), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

Abstract: In the method, trenches (9) are etched and, in between, bit lines (8) are in each case arranged on doped source drain/regions (3). Dopant is introduced into the bottoms of the trenches (9) in order to form doped regions (23), in order to electrically modify the channel regions. Storage layers are applied and gate electrodes (2) are arranged at the trench walls. The semiconductor material at the bottoms of the trenches is etched away between the word lines (18/19) to an extent such that the doped regions (23) are removed there to such a large extent that a crosstalk between adjacent memory cells along the trenches is reduced.

Abstract: The invention relates to a device for setting an operating point of a magnetic field sensor having a periodic characteristic, in particular for a device for detecting a magnetic field and/or flux, having a SQUID as magnetic field sensor and a control unit which is connected downstream of the SQUID, has a control time constant (t) and has a feedback loop which acts on the SQUID and is designed such that it is active about a number of operating points of the SQUID, where flux quantum pump means are provided which are assigned to the SQUID, have a signal generation unit for generating a control and/or regulation signal for the SQUID and are designed such that, in order to pump at least one flux quantum into and out of the SQUID, a signal form of the control and/or regulation signal, generated by the signal generation unit, is different and, referred to a rising and a falling edge of a signal form, is unsymmetrical, where in each case only one of the edges of a signal form is short referred to the control time co