Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract: An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).

Abstract: In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations (7) that are widened for division into slices. Instead of this, the interconnects present below a bit line may be omitted or two mutually adjacent bit lines (41, 42) may be wired up in such a way that the memory transistors present between them operate only in the dummy mode.

Abstract: In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.

Abstract: Electrically conductive material is introduced into interspaces between the word lines (2) and is partially removed using a mask (6) in such a way that residual portions (7) of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (15). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.

Abstract: The invention relates to a device for setting an operating point of a magnetic field sensor having a periodic characteristic, in particular for a device for detecting a magnetic field and/or flux, having a SQUID as magnetic field sensor and a control unit which is connected downstream of the SQUID, has a control time constant (t) and has a feedback loop which acts on the SQUID and is designed such that it is active about a number of operating points of the SQUID, where flux quantum pump means are provided which are assigned to the SQUID, have a signal generation unit for generating a control and/or regulation signal for the SQUID and are designed such that, in order to pump at least one flux quantum into and out of the SQUID, a signal form of the control and/or regulation signal, generated by the signal generation unit, is different and, referred to a rising and a falling edge of a signal form, is unsymmetrical, where in each case only one of the edges of a signal form is short referred to the control time co

Abstract: Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.

Abstract: A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.

Abstract: In a matrix-shaped configuration of memory transistors, word lines are disposed on a top side of a semiconductor body and are parallel to one another. Bit lines run transversely with respect thereto and are formed by polysilicon strips which are applied on the top side and are isolated from the semiconductor body by barrier layers functioning as diffusion barriers.

Abstract: Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 1017 cm−3.

Abstract: Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates are set at a voltage of the same polarity as the programming voltage and at a magnitude of about half the programming voltage. The source is allowed to float and the drain (bitline) and body are set at a low level and at a polarity opposite to the programming voltage polarity.

Abstract: Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 1017 cm−3.

Abstract: A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.

Abstract: A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.

Abstract: Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates are set at a voltage of the same polarity as the programming voltage and at a magnitude of about half the programming voltage. The source is allowed to float and the drain (bitline) and body are set at a low level and at a polarity opposite to the programming voltage polarity.

Abstract: A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.

Abstract: A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.

Abstract: A non-volatile semiconductor memory cell and an associated method are disclosed, in which a conventional dielectric ONO layer (10) is replaced by a very thin metal oxide layer (6) of WOx and/or TiO2. The high relative dielectric constant of these materials further improves the integration density and the control voltages required for the semiconductor memory cell.

Abstract: A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.