Abstract: Masks having various types of structures, such as CPL, HTPSM, or CoG structures, are without positional error with respect to one another by defining positions of the structures on the mask by a single mask lithography step. A patterned absorber layer forms in a first region, the opaque and transparent sections of the CoG structures and, in a second region, the CPL structures by serving as a hard mask for the etching of the CPL structures for example, as trenches in the mask substrate.

Abstract: In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.

Abstract: One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

Abstract: A method of focus variation is described herein to achieve a one-step exposure of a wafer without the limitation of applying a complex y-tilt to a wafer stage. The position of the wafer surface to be exposed is periodically varied with respect to the focal plane, or vice versa. This relative movement between the focal plane, or best focus position along the optical axis and the wafer stage, or the wafer surface, is achieved by applying a movement to at least one of the reticle stage, one or more of the optical elements of the projection lens, and the wafer stage. The frequency of the movement is selected in dependence of the laser frequency (upper limit) or the scanning frequency (lower limit).

Abstract: A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.

Abstract: A semiconductor device with a substrate includes a structure. The structure has a first part and a second part. At least one section of the edge of the first part of the structure is at an essential constant distance measured parallel to the substrate to a first section of an edge of a second structure. At least one section of the edge of the second part of the structure is lined with an edge of a second section of the same second section. The first section of the edge of the second structure and a second section of the edge of the second structure merge at least at one point, whereby the angle between the tangents of the edges of the first and second section of the second structure is less than 90°. The structure and the second structure are distanced by a spacer structure.

Abstract: The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

Abstract: The invention relates to a method for optimizing a mask layout pattern comprising at least one structural feature. First a desired layout pattern is provided. Based on the desired layout pattern, an optimized reference diffraction coefficient is provided. After selecting an initial mask geometry having polygon-shaped structures, initial diffraction coefficients are calculated. A difference based on the reference diffraction coefficient and initial diffraction coefficients is used to optimize the initial geometry in order to provide a mask layout pattern.

Abstract: Semitransparent and trenchlike, absorber-free structure elements are formed jointly on a photomask formed using phase mask technology. The trenchlike structure elements are formed as trench or mesa structure using CPL technology. In a layout, dense, but also if appropriate semi-isolated and isolated, but relatively thin pattern portions are selected to fabricate them on the photomask using CPL technology. By contrast, isolated, wider pattern portions are formed as semitransparent structure elements using halftone phase mask technology. The respective process windows are relatively large and are adapted to one another. The joint process window is enlarged. In the area of dynamic memory chips, structures in a memory cell array can be formed using CPL technology and the support regions using halftone phase mask technology. In logic circuits, thin conductor tracks using CPL technology and wider conductor tracks using halftone phase mask technology can be fabricated.

Abstract: The invention is concerned with a method for manufacturing a local wiring in a semiconductor device, comprising the manufacturing of at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a gap filled with at least one dielectric material, the gap being electrically bridged by conductive material, to form at least one contact element electrically connecting the at least two electrically conducting structures, whereby at least one contact element is produced in a single lithographic step.

Abstract: A method is used for processing a structure of a semiconductor component. The structure has at least one partial structure to be etched, in particular a sublithographic partial structure. The at least one partial structure has at least one structure to be etched with at least one lateral etch stop to which at least one mask is applied in such a way that at least one lateral etch stop is covered by the mask and afterward at least one of the structures to be etched is etched away isotropically as far as at least one etch stop using the mask. The at least one mask and the at least one etch stop are then removed.

Abstract: The invention is concerned with a filter system for a light source in a lithography process for the production of semiconductor devices with a flowing absorber gas for at least one wavelength (?) in the range between 20 to 250 nm, the flowing absorber gas intersecting the light path emitted by the light source. Furthermore, the invention is concerned with a lithography apparatus for processing semiconductor substrates, the use of a filter system, a method for filtering light and a semiconductor device manufactured by the method.

Abstract: A method for forming a structure element in a layer arranged on a wafer by a trimming mask set, a developing step, and an etching step for the transfer of the structure pattern are carried out between the exposure steps carried out by the masks. Consequently, edges that are incipiently exposed below a limit value for the structure formation around the resist structures in a first resist layer, which are exposed using a first mask of the set, are transferred dimensionally accurately into an underlying layer on the wafer. Then, the exposure postprocesses the pattern of the first mask using a second mask of the set, the trimming mask, into a second, subsequently applied second resist layer.

Abstract: A semiconductor wafer is exposed with a pattern from a mask or reticle in an exposure tool. The exposure tool has an adjustable lens system and a light source, which is tunable in wavelength. A first exposure is performed with a tuned first wavelength and a first setting of the lenses. Prior to performing a second exposure onto the same wafer and into the same resist layer, the wavelength of the light source is varied to a second wavelength in order to mimic a focus offset. A resulting image shift at the slit edges of the scanning system due to chromatic aberration is then corrected for by setting the lens system in dependence of the difference between the tuned first and second wavelength. Having tuned second wavelength of the light source and having set the lens system, the second exposure is performed. A continuous adjustment of the lens system based upon a continuously varying light source wavelength can be accomplished.

Abstract: The invention relates to a device for the storage of at least one photomask for lithographic projection and a method for using the device in an exposure installation. A container is suitable for receiving a photomask. The container has a housing, a closable opening device situated at the container housing and serving for the entry and issuing of the photomask, and one gas inlet opening arranged to purge the photomask. The invention also relates to a method for using the device in an exposure installation.

Abstract: In a preferred embodiment, a photosensitive coating material for use as a contrast enhancing layer (CEL) disposed at the bottom of a resist film includes a base polymer, which has no acid cleavable groups for being insoluble with respect to a developer, wherein the developer is designed to remove exposed portions of the resist film. The CEL material further has a solvent for facilitating deposition of the photosensitive coating material upon a surface of a substrate. In one embodiment, the CEL further includes a photolytic acid generator, which is arranged to release an acid under exposure, said acid being arranged to diffuse into the adjacent resist deposited upon the CEL in order to enhance an acid concentration formed in exposed portions of the resist. In another embodiment, the CEL includes an alkaline additive, which is arranged to be photodecomposable to a non-alkaline, neutral compound under exposure.

Abstract: A photosensitive coating material for enhancing a contrast of a photolithographic exposure of a resist film formed on a substrate, including a base polymer, a solvent for facilitating deposition of the photosensitive coating material upon a surface adjacent to said resist film to form a film thereupon, an alkaline additive suited to diffuse into the adjacent resist for reducing or neutralizing an acid concentration formed locally therein, a photoactive component arranged to reduce or neutralize a concentration of the alkaline additives in portions of the photosensitive coating, which are exposed with optical light, UV- or X-ray radiation, electrons, charged particles, ion projection lithography.

Abstract: A photosensitive coating material for enhancing a contrast of a photolithographic exposure of a resist film formed on a substrate, including a base polymer, a solvent for facilitating deposition of the photosensitive coating material upon a surface adjacent to said resist film to form a film thereupon, an alkaline additive suited to diffuse into the adjacent resist for reducing or neutralizing an acid concentration formed locally therein, a photoactive component arranged to reduce or neutralize a concentration of the alkaline additives in portions of the photosensitive coating, which are exposed with optical light, UV- or X-ray radiation, electrons, charged particles, ion projection lithography.

Abstract: A method is provided for improving a photolithographic simulation model of the photolithographic simulation of a pattern formed on a photomask. Proceeding from a two-dimensional simulation model that takes account of the physical-chemical processes during lithography, a frequency-dependent intensity loss is calculated which is determined by multiplication of the simulated intensity distribution in the Fourier space by a filter function. An accurate calculation of the intensity distribution in the substrate plane is obtained. This method achieves the accuracy of three-dimensional models with a significantly shorter processing duration and is further suitable in particular for the calculation of OPC structures.

Abstract: The invention relates to a method for optimizing a mask layout pattern comprising at least one structural feature. First a desired layout pattern is provided. Based on the desired layout pattern, an optimized reference diffraction coefficient is provided. After selecting an initial mask geometry having polygon-shaped structures, initial diffraction coefficients are calculated. A difference based on the reference diffraction coefficient and initial diffraction coefficients is used to optimize the initial geometry in order to provide a mask layout pattern.