Abstract: Embodiments herein describe a PIM correction circuit. In a base station, TX and RX RF changes, band pass filters, duplexers, and diplexers can have severe memory effects due to their sharp transition bandwidth from pass band to stop band. PIM interference, generated by the TX signals and reflected onto the RX RF chain will include these memory effects. These memory effects make PIM cancellation complex, requiring complicated computations and circuits. However, the embodiments herein use a PIM correction circuit that separates the memory effects of the TX and RX paths from the memory effects of PIM, thereby reducing PIM cancellation complexity and hardware implementation cost.

Abstract: Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.

Abstract: Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.

Abstract: A biasing scheme for a voltage-to-time converter (VTC). An example biasing circuit generally includes a reference current source; a feedback loop current source; an amplifier having a first input coupled to a target voltage node, having a second input, and having an output coupled to a control input of the reference current source and to a control input of the feedback loop current source; a first capacitive element; a first switch coupled in parallel with the first capacitive element; a second switch coupled between the feedback loop current source and the first capacitive element; and a third switch coupled between the first capacitive element and the second input of the amplifier.

Abstract: Embodiments herein describe adapting a PIM model to compensate for changing PIM interference. A PIM model can include circuitry that generates a PIM compensation value that compensates for (i.e., mitigates or subtracts) PIM interference caused by transmitting two or more transmitter (TX) carriers in the same path. The disclosed adaptive scheme generates updated coefficients for the PIM model which are calculated after the RX signal has been removed from the RX channel. In this manner, as the PIM interference changes due to environmental conditions (e.g., temperature at the base station), the adaptive scheme can update the PIM model to generate a PIM compensation value that cancels the PIM interference.

Abstract: Embodiments herein describe adapting a PIM model to compensate for changing PIM interference. A PIM model can include circuitry that generates a PIM compensation value that compensates for (i.e., mitigates or subtracts) PIM interference caused by transmitting two or more transmitter (TX) carriers in the same path. The disclosed adaptive scheme generates updated coefficients for the PIM model which are calculated after the RX signal has been removed from the RX channel. In this manner, as the PIM interference changes due to environmental conditions (e.g., temperature at the base station), the adaptive scheme can update the PIM model to generate a PIM compensation value that cancels the PIM interference.

Abstract: A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive? voltage, respectively. The circuit further includes a first diode connected transistor (“DCT”) coupled to the second input interface, a first switching transistor (“ST”) coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.

Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

Abstract: A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of analog-to-digital converters (ADCs) to sample the reflected pulses in response to the clock signal. Accordingly, the ADCs are locked in phase with the DACs.

Abstract: An apparatus for generating an output current including a first distortion current based on a first transconductance and a second distortion current based on a second transconductance is disclosed. The first distortion current may be generated by an amplifier and the second distortion current may be generated by a distortion compensator. The second transconductance may be less than the first transconductance. In some implementations, the second distortion current may reduce the first distortion current output by the apparatus.

Abstract: An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.

Abstract: A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.

Abstract: Apparatus and associated methods relate to maintaining a total current of a switch cell in a digital-to-analog converter at a controllable operating point by adjusting shunt current control signals applied to programmable shunt current sources in opposite polarity with respect to a tail current control signal applied to a programmable tail current source. In an illustrative example, the total current may flow through differential legs of a switch cell. The programmable shunt current sources may, for example, be configured to compensate for adjustments to the programmable tail current source. In an illustrative example, tail current and shunt currents may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current sources to compensate adjustments to the tail current source may, for example, permit controlled common mode voltage or operating point so as to reduce device voltage stress over a wider dynamic range of output voltages.

Abstract: A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of analog-to-digital converters (ADCs) to sample the reflected pulses in response to the clock signal. Accordingly, the ADCs are locked in phase with the DACs.

Abstract: Apparatus and associated methods relating to a switch leakage compensation delay circuit include a compensating transistor configured to passively bypass a leakage current around a capacitor that connects in series with a control transistor. In an illustrative example, the capacitor and the compensating transistor may be connected in parallel between a first node and a second node. The compensating transistor gate may be tied, for example, directly to its source and to the second node. The control transistor may connect its drain to the second node. When a control signal turns off the control transistor, a leakage current of the control transistor may be supplied from a leakage current of the compensating transistor such that the voltage across the capacitor may be maintained substantially constant. The delay circuit may advantageously mitigate the capacitor's voltage droop to reduce clock time skew, for example, in low speed interleaved ADC operation.

Abstract: Apparatus and associated methods relating to a digital-to-analog converter (DAC) include a programmable resistance network coupled between a voltage supply node VDD and a switch cell circuit to provide a predetermined resistance in response to the VDD and current IS of the switch cell circuit. In an illustrative example, the DAC may include a switch cell circuit comprising one or more switch cells connected in parallel. Each switch cell may include a differential gain circuit having a first branch coupled to a second branch at an input of a current source. The programmable resistance may include a variable resistance configured to adjust a voltage (Vbias) supplied to the switch cell circuit in response to a control signal. By introducing the programmable resistance network, predetermined bias and/or gain values may be dynamically adjusted with a constant board-level power supply VDD.

Abstract: Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

Abstract: An integrated circuit is described. The integrated circuit comprises a first portion having programmable resources; a second portion having hardened circuits including an analog-to-digital converter circuit configured to receive an input signal and generate an output signal; and a monitor circuit configured to receive an output signal generated by the analog-to-digital converter circuit; wherein the monitor circuit is configurable to control a calibration of the analog-to-digital converter circuit based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

Abstract: An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.