Abstract: Examples of the present disclosure provide out-of-range voltage detection and protection in integrated circuits (ICs). In some examples, an IC includes an envelope detector, a comparator, and a switch. The envelope detector is configured to generate an envelope signal of a signal and output the envelope signal on an output node of the envelope detector. A first input node of the comparator is coupled to the output node of the envelope detector. The comparator is configured to compare respective signals provided on the first and second input nodes of the comparator and generate a comparison signal in response to the comparison. The comparator is further configured to output the comparison signal on the output node of the comparator. The switch is connected between a protected node and a protection node and is configured to be selectively opened or closed based, at least in part, on the comparison signal.

Abstract: An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

Abstract: An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.

Abstract: An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

Abstract: An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

Abstract: A time-skew adjustment circuit includes an input to receive a series of samples of an input signal from a plurality of channels of an interleaved ADC. A first subtractor calculates distances between consecutive samples in the received series of samples, and a plurality of average circuit code and a plurality of memory banks to calculate a plurality of first average distance, each corresponding to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC. Time-skew detection circuitry calculates respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels. Divergence control circuitry determines an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.

Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

Abstract: An analog to digital converter (ADC) includes a comparator and a plurality of capacitor pairs coupled between first and second inputs the comparator, where each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage. The ADC also includes a voltage detection circuit and a state machine that is configured to, upon determining during a first cycle that the sampled voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs in a default state such that the sampled analog voltage is unchanged. Otherwise, the state machine is configured to switch the first pair of the plurality of capacitor pairs to change the sampled analog voltage.

Abstract: In one example, a current steering circuit for a digital-to-analog converter (DAC) includes a source-coupled transistor pair responsive to a differential gate voltage; a current source coupled to the source-coupled transistor pair operable to source a bias current; a load circuit coupled to the source-coupled transistor pair operable to provide a differential output voltage; a driver having a first input, a second input, and a differential output, the differential output providing the differential gate voltage; and combinatorial logic having a data input, a clock input, a true output, and a complement output, the true output and the complement output respectively coupled to the first input and the second input of the driver, the combinatorial logic operable to exclusively OR a data signal on the data input and a clock signal on the clock input.

Abstract: An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Abstract: An apparatus relating generally to signal analysis is disclosed. In such an apparatus, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. A time-to-digital converter is coupled at a first port thereof, such as a start port for example, to receive a first output from the first comparator and coupled at a second port thereof, such as a stop port for example, to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input.

Abstract: An apparatus relating generally to a current steering cell includes a first bleeder circuit, a second bleeder circuit, a steering circuit, and an output circuit. The first bleeder circuit and the second bleeder circuit are coupled to receive a first current-source bias voltage. The steering circuit is coupled to receive a second current-source bias voltage independent from the first current-source bias voltage.

Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.

Abstract: An exemplary integrated circuit for performing time skew extraction includes a first subtractor, an array of subtractors separate from the first subtractor, and an array of averaging circuits. Inputs of the first subtractor are coupled to outputs of a plurality of channels of an interleaved analog-to-digital-converter and computes distances between samples of a signal that are measured consecutively by pairs of channels in the plurality of channels. At least some averaging circuits in the array of averaging circuits compute an average of those of the distances that correspond to a respective one of the pairs of channels; one averaging circuit in the array of averaging circuits computes an average of all of the distances. Each subtractor in the array of subtractors computes a difference between an average computed by one of the at least some of the averaging circuits and the average of all of the distances.

Abstract: An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Abstract: A method of gain calibration of an ADC stage is provided. The method includes steps of receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The the calibration signal may take any one of three values and may be constrained to one of only two of these three values. An ADC stage adapted to operate according to the method is also provided.

Abstract: A method of calibrating a pipelined analog to digital converter having a plurality of DAC elements and an additional calibration DAC element is provided. In the method as provided herein, a combination of positive, negative and zero reference voltages are applied to the element under calibration and positive and negative reference voltages are applied to the additional calibration DAC element to obtain four calibration states. An error of the DAC element under calibration is extracted by calculating an average of the difference between the four calibration states.

Abstract: A method of gain calibration of an ADC stage is disclosed. The method comprises receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The method is characterised in that the calibration signal may take any one of three values. In a preferred embodiment, the calibration is constrained to one of only two of these three values, when the input signal is in an outermost sub-range. An ADC stage adapted to operate according to the method is also disclosed.

Abstract: A method of calibrating a pipelined analog to digital converter (400) having a plurality of DAC elements (410) and an additional calibration DAC element (420), in which a combination of positive, negative and zero reference voltages to the element under calibration and positive and negative reference voltages to the additional calibration DAC element to obtain four calibration states from which an error of the element under calibration is extracted by calculating an average of the difference between the four calibration states.