Patents by Inventor Christophe Frey
Christophe Frey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7696649Abstract: The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal and responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level.Type: GrantFiled: August 13, 2007Date of Patent: April 13, 2010Assignee: ARM LimitedInventors: Christophe Frey, Andrew John Sowden
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Publication number: 20090045677Abstract: A power control circuitry and method of operation are provided for controlling the connection of a voltage source to an associated circuit when that circuit is to enter an active state of operation. The associated circuit has a plurality of circuit portions, and each circuit portion has at least one voltage line for connection to the voltage source. The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal. Each power switching circuit is responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series.Type: ApplicationFiled: August 13, 2007Publication date: February 19, 2009Applicant: ARM LimitedInventors: Christophe Frey, Andrew John Sowden
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Patent number: 7372728Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: GrantFiled: April 23, 2007Date of Patent: May 13, 2008Assignees: STMicroelectronics, Inc., STMicroelectronics S.A.Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel
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Patent number: 7301800Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines, the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store information within the element in any one of at least three logic states.Type: GrantFiled: June 30, 2004Date of Patent: November 27, 2007Assignee: STMicroelectronics, Inc.Inventor: Christophe Frey
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Patent number: 7301798Abstract: A memory cell (1), includes a flip-flop (2) that has additional read/write terminals; a 1-bit write line (wb11); a first transistor (T4) switching between the 1-bit write line and the terminal, its gate being connected to a word selection line (W11); a 0-bit write line (wb10); a second transistor (T3) switching between the 0-bit write line and the terminal, its gate being connected to a word selection line (W12); a bit read line (b1r); and read transistors (T1, T2), with one of their gates being connected to a read/write terminal and the other being connected to a word selection line.Type: GrantFiled: June 16, 2005Date of Patent: November 27, 2007Assignee: STMicroelectronics S.A.Inventors: Christophe Frey, David Turgis, Jean-Christophe Lafont
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Publication number: 20070189066Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: ApplicationFiled: April 23, 2007Publication date: August 16, 2007Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sebastien Barasinski, Richard Fournel
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Patent number: 7209383Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: GrantFiled: June 23, 2005Date of Patent: April 24, 2007Assignee: STMicroelectronics, Inc.Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel
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Patent number: 7139212Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.Type: GrantFiled: June 14, 2005Date of Patent: November 21, 2006Assignee: STMicroelectronics S.A.Inventors: Cyrille Dray, Sébastien Barasinski, Jean Lasseuguette, Christophe Frey, Richard Fournel
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Patent number: 7136298Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row group share a common local write digit line and the elements in each column group share a common local write bit line. The array further includes at least one global write digit line coupled to the common local write digit lines of plural row groups, and at least one global write bit line coupled to the common local write bit lines of plural column groups.Type: GrantFiled: June 30, 2004Date of Patent: November 14, 2006Assignee: STMicroelectronics, Inc.Inventor: Christophe Frey
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Patent number: 7106621Abstract: A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells.Type: GrantFiled: June 30, 2004Date of Patent: September 12, 2006Assignee: STMicroelectronics, Inc.Inventor: Christophe Frey
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Patent number: 7079415Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.Type: GrantFiled: June 30, 2004Date of Patent: July 18, 2006Assignee: STMicroelectronics, Inc.Inventor: Christophe Frey
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Patent number: 7050348Abstract: An integrated circuit includes a memory, and the memory includes a memory plane arranged in rows and columns, and a plurality of read amplifiers connected to the columns of the memory plane. A reference path includes first and second reference columns, and a reference memory cell is connected between the first and second reference columns. A reference row is connected to the reference memory cell for selection thereof so that the first reference column conducts a discharge current and the second reference column conducts a leakage current. A control circuit is connected between the first and second reference columns and the read amplifiers. The control circuit provides an activation signal to the read amplifiers when an absolute value of a difference between voltages on the first and second reference columns exceeds a threshold.Type: GrantFiled: June 29, 2004Date of Patent: May 23, 2006Assignee: STMicroelectronics SAInventors: Christophe Frey, Franck Genevaux
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Publication number: 20060002191Abstract: A memory cell (1), includes: a flip-flop (2) that has additional read/write terminals; a 1-bit write line (wb11); a first transistor (T4) switching between the 1-bit write line and the terminal, its gate being connected to a word selection line (W11); a 0-bit write line (wb10); a second transistor (T3) switching between the 0-bit write line and the terminal, its gate being connected to a word selection line (W12); a bit read line (b1r); and read transistors (T1, T2), with one of their gates being connected to a read/write terminal and the other being connected to a word selection line. The invention particularly allows the surface area and complexity of a memory cell to be reduced.Type: ApplicationFiled: June 16, 2005Publication date: January 5, 2006Applicant: STMICROELECTRONICS SAInventors: Christophe Frey, David Turgis, Jean-Christophe Lafont
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Publication number: 20060002186Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Applicant: STMicroelectronics, Inc.Inventor: Christophe Frey
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Publication number: 20060002180Abstract: A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Applicant: STMicroelectronics, Inc.Inventor: Christophe Frey
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Publication number: 20060002181Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row group share a common local write digit line and the elements in each column group share a common local write bit line. The array further includes at least one global write digit line coupled to the common local write digit lines of plural row groups, and at least one global write bit line coupled to the common local write bit lines of plural column groups.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Applicant: STMicroelectronics, Inc.Inventor: Christophe Frey
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Publication number: 20060002182Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines, the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store information within the element in any one of at least three logic states.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Applicant: STMicroelectronics, Inc.Inventor: Christophe Frey
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Publication number: 20050281090Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.Type: ApplicationFiled: June 14, 2005Publication date: December 22, 2005Applicant: STMicroelectronics S.A.Inventors: Cyrille Dray, Sebastien Barasinski, Jean Lasseuguette, Christophe Frey, Richard Fournel
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Publication number: 20050281080Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: ApplicationFiled: June 23, 2005Publication date: December 22, 2005Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sebastien Barasinski, Richard Fournel
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Publication number: 20050018498Abstract: An integrated circuit includes a memory, and the memory includes a memory plane arranged in rows and columns, and a plurality of read amplifiers connected to the columns of the memory plane. A reference path includes first and second reference columns, and a reference memory cell is connected between the first and second reference columns. A reference row is connected to the reference memory cell for selection thereof so that the first reference column conducts a discharge current and the second reference column conducts a leakage current. A control circuit is connected between the first and second reference columns and the read amplifiers. The control circuit provides an activation signal to the read amplifiers when an absolute value of a difference between voltages on the first and second reference columns exceeds a threshold.Type: ApplicationFiled: June 29, 2004Publication date: January 27, 2005Applicant: STMicroelectronics SAInventors: Christophe Frey, Franck Genevaux