Patents by Inventor Christophe J. Chevallier

Christophe J. Chevallier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM with multiple power domains
    Patent number: 10347328
    Abstract: An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 9, 2019
    Assignee: Ambiq Micro, Inc.
    Inventors: Christophe J. Chevallier, Scott Hanson
  • Memory element with a reactive metal layer
    Patent number: 10340312
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 2, 2019
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Method and apparatus for controlling substrate and well biases for reduced power requirements
    Patent number: 10332589
    Abstract: An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Ambiq Micro, Inc.
    Inventors: Scott Hanson, Christophe J. Chevallier
  • SRAM with error correction in retention mode
    Patent number: 10319429
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 11, 2019
    Assignee: AMBIQ MICRO, INC.
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
    Publication number: 20190173006
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: January 30, 2019
    Publication date: June 6, 2019
    Inventors: Darrell RINERSON, Christophe J. CHEVALLIER, Wayne KINNEY, Roy LAMBERTSON, John E. SANCHEZ, JR., Lawrence SCHLOSS, Philip SWAB, Edmond WARD
  • Write assist thyristor-based SRAM circuits and methods of operation
    Patent number: 10283185
    Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 7, 2019
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
  • SRAM with Error Correction in Retention Mode
    Publication number: 20190074056
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Application
    Filed: May 17, 2018
    Publication date: March 7, 2019
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • Two-terminal reversibly switchable memory device
    Patent number: 10224480
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • SRAM With Address Dependent Power Usage
    Publication number: 20190019550
    Abstract: A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.
    Type: Application
    Filed: July 12, 2017
    Publication date: January 17, 2019
    Inventor: Christophe J. Chevallier
  • SRAM WITH MULTIPLE POWER DOMAINS
    Publication number: 20180336945
    Abstract: An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Christophe J. Chevallier, Scott Hanson
  • SRAM with error correction in retention mode
    Patent number: 10096354
    Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: October 9, 2018
    Assignee: AMBIQ MICRO, INC.
    Inventors: Christophe J. Chevallier, Stephen James Sheafor
  • SRAM with multiple power domains
    Patent number: 10062431
    Abstract: An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: August 28, 2018
    Assignee: Ambiq Micro, Inc.
    Inventors: Christophe J. Chevallier, Scott Hanson
  • Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
    Patent number: 10056389
    Abstract: A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 21, 2018
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
  • Low Power Buffer with Voltage Conversion
    Publication number: 20180226972
    Abstract: A voltage conversion circuit and method that includes applying a positive bias to a PMOS gate to source voltage and/or a negative bias to an NMOS gate to source voltage. These biases serve to further reduce the leakage current of the unselected device of a driver while in standby mode, as well as convert an input signal at one voltage potential to an output voltage at a different voltage potential.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 9, 2018
    Inventor: Christophe J. Chevallier
  • SRAM WITH ACTIVE SUBSTRATE BIAS
    Publication number: 20180211702
    Abstract: An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.
    Type: Application
    Filed: October 12, 2017
    Publication date: July 26, 2018
    Applicant: Ambiq Micro, Inc.
    Inventors: Scott Hanson, Christophe J. Chevallier
  • SRAM With Multiple Power Domains
    Publication number: 20180130520
    Abstract: An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.
    Type: Application
    Filed: November 7, 2016
    Publication date: May 10, 2018
    Applicant: Ambiq Micro, Inc.
    Inventors: Christophe J. Chevallier, Scott Hanson
  • TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
    Publication number: 20180130946
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 10, 2018
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • MEMORY ELEMENT WITH A REACTIVE METAL LAYER
    Publication number: 20180122857
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 3, 2018
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Two-transistor SRAM semiconductor structure and methods of fabrication
    Patent number: 9899389
    Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: February 20, 2018
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng, Christophe J. Chevallier
  • SRAM with active substrate bias
    Patent number: 9830974
    Abstract: An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: November 28, 2017
    Assignee: Ambiq Micro, Inch
    Inventors: Scott Hanson, Christophe J. Chevallier