Abstract: A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.

Abstract: A method for performing error recovery that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.

Abstract: A computer program product for performing error recovery is configured to perform a method that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.

Abstract: Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

Abstract: Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

Abstract: Threads of a computing environment are managed to improve system performance. Threads are migrated between processors to take advantage of single thread processing mode, when possible. As an example, inactive threads are migrated from one or more processors, potentially freeing-up one or more processors to execute an active thread. Active threads are migrated from one processor to another to transform multiple threading mode processors to single thread mode processors.

Abstract: According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test generation tool executed by a computer. The method further includes generating an instruction sequence based on the test template by the automated test generation tool and injecting an event instruction to the instruction sequence during the generating of the instruction sequence by the automated test generation tool, the injecting of the event instruction preserving testing of the first selected function of the processor and the event instruction being configured to test a second selected function of the processor. The method includes verifying a function of the processor by analyzing responses of the processor to the instruction sequence.

Abstract: A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.

Abstract: A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.

Abstract: Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.

Abstract: A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware.

Abstract: A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initialization of instruction code into the SMC trap source.

Abstract: A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.

Abstract: Systems, methods and computer program products for exploiting orthogonal control vectors in timing driven systems. An exemplary embodiment includes running an initial logic synthesis run on the system, identifying critical inputs to a logic cone related to the run, identifying orthogonal vectors in the logic cone, adding vectors to the logic cone, obtaining logical solutions and selecting a solution from the logical solutions.

Abstract: Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wher

Abstract: System, method and computer program products for failure analysis implementing automated comparison of multiple reference models. An exemplary embodiment includes a method for failure analysis for an instruction set implementation in a computer system, the method including running a test-case in a first and a second model, determining if the test case failed in the first model and determining if the test case failed in the second model.

Abstract: A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

Abstract: Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wher

Abstract: Systems, methods and computer program products for exploiting orthogonal control vectors in timing driven systems. An exemplary embodiment includes running an initial logic synthesis run on the system, identifying critical inputs to a logic cone related to the run, identifying orthogonal vectors in the logic cone, adding vectors to the logic cone, obtaining logical solutions and selecting a solution from the logical solutions.

Abstract: System, method and computer program products for failure analysis implementing automated comparison of multiple reference models. An exemplary embodiment includes a method for failure analysis for an instruction set implementation in a computer system, the method including running a test-case in a first and a second model, determining if the test case failed in the first model and determining if the test case failed in the second model.