Abstract: To make a branch prediction, a branch prediction apparatus determines a trigger load instruction whose value feeds into the branch instruction. A hash value is associated with the branch instruction. The branch prediction apparatus computes the hash value based on the trigger load instruction. If the hash value has not changed, the branch prediction apparatus predicts the branch to be chosen based on past predictions for the hash value.

Abstract: A prefetch engine is responsible for prefetching critical data. The prefetch engine operates when a cache miss occurs accessing critical data requested by a processor. The prefetch engine requests cache lines surrounding the cache line satisfying the data request be loaded into the cache.

Abstract: A load instruction is classified as vital or non-vital. One of a number of caches with different latencies is selected, based on a vitality of the load instruction. Data are then loaded through the selected cache into a register in a microprocessor.

Abstract: The critical cache tracks a critical score for each cache line in the critical cache. On cache hits, the critical score of the hit cache line is incremented by an instance score assigned to the data request. On cache misses, data may be retrieved from main memory without allocating a cache line into the critical cache, in which case the instance score is subtracted from the critical scores of all cache lines in the cache. Alternatively on a cache miss, the cache line with the smallest critical score is removed from the cache. The smallest critical score is then subtracted from each cache line in the critical cache. A new cache line is allocated that satisfies the data request, and the new cache line is given the instance score of the data request as a critical score.

Abstract: System and method to reduce execution of instructions involving unreliable data in a speculative processor. A method comprises identifying scratch values generated during speculative execution of a processor, and setting at least one tag associated with at least one data area of the processor to indicate that the data area holds a scratch value. Such data areas include registers, predicates, flags, and the like. Instructions may also be similarly tagged. The method may be executed by an execution engine in a computer processor.

Abstract: A spatial footprint predictor includes a mechanism to measure spatial footprints of nominating cache-lines and hold the footprints. In some embodiments, the mechanism includes an active macro-block table (AMBT) to measure the spatial footprints and a spatial footprint table (SFT) to hold the spatial footprints. In other embodiments, the mechanism includes a macro-block table (MBT) in which macro-blocks may be active or inactive.

Abstract: An apparatus may include a first storage location to store a key value of an activated correlated data values (CDV) pair and a second storage location to store a correlated value corresponding to the key value. An apparatus may also include a first storage location to store an instruction to activate a CDV pair and a second storage location to store an instruction to deactivate the CDV pair. A system may comprise a processor to fetch and execute a native instruction set including an instruction to activate a CDV pair and an instruction to deactivate the CDV pair, as well as a memory to store a table that includes the CDV pair. A machine-readable medium may include instructions causing a machine to perform a method comprising activating a CDV pair and performing a first task using the correlated value in parallel with a second task using the key value.

Abstract: A load instruction is classified as vital or non-vital. One of a number of caches with different latencies is selected, based on a vitality of the load instruction. Data are then loaded through the selected cache into a register in a microprocessor.

Abstract: A speculative execution method decreases execution time. A key value and a correlated value are stored as a correlated data values pair. Upon matching a current value to the key value, the correlated value is retrieved. A first thread is executed using the current value to produce a first result. The first result is consumed by a second thread. The second thread is speculatively executed using the correlated value to produce a second result. Upon verifying that the first result is the same as the correlated value, the second result is used. The first and second threads are iterations of a loop. The first and second threads use indirect addressing. The first and second threads use a linked list data structure. Storing the key value and the correlated value as the correlated data values pair comprises storing the correlated data values pair in a lookup table.

Abstract: A method and apparatus are described for protecting cache lines allocated to a cache by a run-ahead prefetcher from premature eviction, preventing thrashing. The invention also prevents premature eviction of cache lines still in use, such as lines allocated by the run-ahead prefetcher but not yet referenced by normal execution. A protection bit indicates whether its associated cache line has protected status in the cache or whether it may be evicted.

Abstract: Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for each successor value entered into the correlation table. In a second embodiment, correlation prediction tables of the present invention utilize address offsets for both the entered keys and entered successor values.

Abstract: Apparatus and methods are disclosed for inputting and rendering haptic data. Wherein, a haptel generates a signal in response to subjecting the haptel to a stimulus.

Abstract: Set address correlation correlates between addresses belonging to a common address set. Addresses are grouped into address sets and correlations are created between addresses by set. The correlations are used to predict future addresses based on current addresses.

Abstract: To make a branch prediction, a branch prediction apparatus determines a trigger load instruction whose value feeds into the branch instruction. A hash value is associated with the branch instruction. The branch prediction apparatus computes the hash value based on the trigger load instruction. If the hash value has not changed, the branch prediction apparatus predicts the branch to be chosen based on past predictions for the hash value.

Abstract: A spatial footprint predictor includes a mechanism to measure spatial footprints of nominating cache-lines and hold the footprints. In some embodiments, the mechanism includes an active macro-block table (AMBT) to measure the spatial footprints and a spatial footprint table (SFT) to hold the spatial footprints. In other embodiments, the mechanism includes a macro-block table (MBT) in which macro-blocks may be active or inactive.

Abstract: An LRU with protection method is provided that offers substantial performance benefits over traditional LRU replacement methods by providing solutions to common problems with traditional LRU replacement. By dividing a cache entry list into a filter sublist and a reuse list, population and protection processes can be implemented to reduce associativity and capacity displacement. New cache entries are initially stored in the filter list, and the reuse list is populated with entries promoted from the cache list. Eviction from the filter list and reuse list is done by a protection process that evicts a data entry from the filter, reuse, or global cache list. Many variations of protection and eviction processes are discussed herein, along with the benefits each provides in reducing the effect of unwanted displacement problems present in traditional LRU replacement.

Abstract: Parallel processing utilizing correlated data values. One embodiment of the invention includes a method. The method renders active a correlated data values pair comprising a key value and a value correlated with the key value. The method next performs a task utilizing the value correlated with the key value in parallel with the task utilizing the key value. The method then renders inactive the correlated data values pair.

Abstract: The decomposition of instructions into separate sequential and branch instruction code sections. In one embodiment, a system including a first store to store a first code section including only branch instructions and a second store to store a second code section including only sequential instructions. In another embodiment, the system also includes a processor having a first engine to process the branch instructions, and a second engine to process the sequential instructions.