Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

Abstract: Examples may include techniques for adaptive compression for data stored in a memory device. The techniques include monitoring a data access pattern to a file or a block for data stored in the memory device and determining a data compression action based on, at least in part, the monitored data access patterns for the file or the block and on an assessed relationship of the file or the block with other files or other blocks. The data compression action including compressing data accessed via the file or the block, decompressing compressed data accessed via the file or the block or no compression action for data accessed via the file or the block.

Abstract: An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

Abstract: An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

Abstract: A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

Abstract: Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.

Abstract: A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

Abstract: In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.

Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract: A system and method to enforce read-write partitioning in an N-way, set associative cache may limit a number of ways allocated for storing modified data in a set to a value W and limit a number of ways holding read data to a value R. The cache may be configured where N=R+W. Furthermore, a number of ways storing prefetched read data may be limited to RP, while a number of ways storing prefetched modified data may be limited to WP. The values for W, R, WP, and/or RP may be determined using a prediction method to estimate cache miss rates for different values for W, R, WP, and/or RP and selecting values corresponding to a desired cache miss rate, and so allowing for selective application of the read-write partitioning.

Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract: An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

Abstract: A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

Abstract: In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.

Abstract: Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged.

Abstract: Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory.

Abstract: Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.

Abstract: Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.

Abstract: A system and method to enforce read-write partitioning in an N-way, set associative cache may limit a number of ways allocated for storing modified data in a set to a value W and limit a number of ways holding read data to a value R. The cache may be configured where N=R+W. Furthermore, a number of ways storing prefetched read data may be limited to RP, while a number of ways storing prefetched modified data may be limited to WP. The values for W, R, WP, and/or RP may be determined using a prediction method to estimate cache miss rates for different values for W, R, WP, and/or RP and selecting values corresponding to a desired cache miss rate, and so allowing for selective application of the read-write partitioning.