Patents by Inventor Christopher Boguslaw Kocon

Christopher Boguslaw Kocon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200373424
    Abstract: A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Inventors: Christopher Boguslaw Kocon, Simon John Molloy, John Manning Savidge Neilson, Hideaki Kawahara
  • Publication number: 20200365727
    Abstract: A semiconductor device includes a semiconductor substrate with a trench, a body region under the trench with majority carrier dopants of a first type, and a transistor, including a source region under the trench with majority carrier dopants of a second type, a drain region spaced from the trench with majority carrier dopants of the second type, a gate structure in the trench proximate a channel portion of a body region, and an oxide structure in the trench proximate a side of the gate structure.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 10811533
    Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Hideaki Kawahara, Simon John Molloy, Satoshi Suzuki, John Manning Savidge Neilson
  • Patent number: 10770584
    Abstract: A semiconductor device includes a semiconductor substrate with a trench, a body region under the trench with majority carrier dopants of a first type, and a transistor, including a source region under the trench with majority carrier dopants of a second type, a drain region spaced from the trench with majority carrier dopants of the second type, a gate structure in the trench proximate a channel portion of a body region, and an oxide structure in the trench proximate a side of the gate structure.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 10741684
    Abstract: A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: August 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Simon John Molloy, John Manning Savidge Neilson, Hideaki Kawahara
  • Patent number: 10672901
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 2, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Satoshi Suzuki, Simon John Molloy
  • Publication number: 20200152788
    Abstract: A semiconductor device includes a semiconductor substrate with a trench, a body region under the trench with majority carrier dopants of a first type, and a transistor, including a source region under the trench with majority carrier dopants of a second type, a drain region spaced from the trench with majority carrier dopants of the second type, a gate structure in the trench proximate a channel portion of a body region, and an oxide structure in the trench proximate a side of the gate structure.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Inventor: Christopher Boguslaw Kocon
  • Publication number: 20200152623
    Abstract: An electronic device includes a MOS transistor with a source and a drain, and a capacitor with a first plate connected directly to the source, and a second plate connected directly to the drain. A method to fabricate an electronic device includes fabricating a MOS transistor on or in a semiconductor structure, and fabricating a capacitor having a first plate connected directly to a source of the MOS transistor, and a second plate connected directly to a drain of the MOS transistor.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Applicant: Texas Instruments Incorporated
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 10573718
    Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Simon John Molloy, John Manning Savidge Neilson, Hideaki Kawahara
  • Patent number: 10553717
    Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Hideaki Kawahara, Simon John Molloy, Satoshi Suzuki, John Manning Savidge Neilson
  • Patent number: 10541326
    Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Seetharaman Sridhar, Christopher Boguslaw Kocon, Simon John Molloy, Hong Yang
  • Publication number: 20190259868
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 22, 2019
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Satoshi Suzuki, Simon John Molloy
  • Patent number: 10256337
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: April 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Simon John Molloy, Satoshi Suzuki
  • Publication number: 20180226502
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Simon John Molloy, Satoshi Suzuki
  • Patent number: 9905638
    Abstract: A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at an etching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tatsuya Tominari, Satoshi Suzuki, Seetharaman Sridhar, Christopher Boguslaw Kocon, Simon John Molloy, Hideaki Kawahara
  • Patent number: 9905428
    Abstract: A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Andrew D Strachan, Alexei Sadovnikov, Christopher Boguslaw Kocon
  • Patent number: 9881995
    Abstract: A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abuts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 30, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, John Manning Savidge Neilson
  • Publication number: 20170288052
    Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 5, 2017
    Inventors: Hideaki Kawahara, Seetharaman Sridhar, Christopher Boguslaw Kocon, Simon John Molloy, Hong Yang
  • Publication number: 20170222041
    Abstract: A method of fabricating a semiconductor device includes etching a semiconductor substrate having a top surface to form a trench having sidewalls and a bottom surface that extends from the top surface into the semiconductor substrate. A dielectric liner of a first dielectric material is formed on the bottom surface and sidewalls of the trench to line the trench. A second dielectric layer of a second dielectric material is deposited to at least partially fill the trench. The second dielectric layer is partially etched to selectively remove the second dielectric layer from an upper portion of the trench while preserving the second dielectric layer on a lower portion of the trench. The trench is filled with a fill material which provides an electrical conductivity that is at least that of a semiconductor.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 3, 2017
    Inventors: HIDEAKI KAWAHARA, HONG YANG, CHRISTOPHER BOGUSLAW KOCON, YUFEI XIONG, YUNLONG LIU
  • Patent number: 9711639
    Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Seetharaman Sridhar, Christopher Boguslaw Kocon, Simon John Molloy, Hong Yang