Patents by Inventor Christopher C. Parks
Christopher C. Parks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941191Abstract: Button functionalities for user interfaces, e.g., for use with a portable multifunction device, are disclosed. Exemplary button functionalities are described for an electronic device with a display, a rotatable and depressible input mechanism, and/or a button. Different device features may be accessed, depending on whether the rotatable and depressible input mechanism or the button is activated, and further depending on whether the activation represents a single press, a double press, or an extended press on the rotatable and depressible input mechanism or the button.Type: GrantFiled: May 5, 2023Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Christopher Patrick Foss, Anton M. Davydov, Dylan Ross Edwards, Imran Chaudhri, Alan C. Dye, Jonathan P. Ive, Stephen O. Lemay, Kevin M. Lynch, Lawrence Y. Yang, Dennis S. Park
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Patent number: 10483205Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.Type: GrantFiled: February 22, 2018Date of Patent: November 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Donghun Kang, Neal A. Makela, Christopher C. Parks
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Publication number: 20180182711Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.Type: ApplicationFiled: February 22, 2018Publication date: June 28, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Donghun Kang, Neal A. Makela, Christopher C. Parks
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Patent number: 9960118Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.Type: GrantFiled: January 20, 2016Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Donghun Kang, Neal A. Makela, Christopher C. Parks
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Publication number: 20170207175Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.Type: ApplicationFiled: January 20, 2016Publication date: July 20, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Donghun Kang, Neal A. Makela, Christopher C. Parks
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Patent number: 8563446Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.Type: GrantFiled: May 18, 2012Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
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Patent number: 8431476Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.Type: GrantFiled: August 9, 2012Date of Patent: April 30, 2013Assignee: International Business Machines CorporationInventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
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Patent number: 8415772Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.Type: GrantFiled: August 9, 2012Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
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Publication number: 20120309153Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.Type: ApplicationFiled: August 9, 2012Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
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Publication number: 20120305989Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.Type: ApplicationFiled: August 9, 2012Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
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Patent number: 8273649Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.Type: GrantFiled: November 17, 2008Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
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Publication number: 20120228736Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
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Patent number: 8236710Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.Type: GrantFiled: October 7, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
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Publication number: 20120086103Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Applicant: International Business Machines CorporationInventors: ASHIMA B. CHAKRAVARTI, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
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Patent number: 7843067Abstract: The present disclosure relates to a microelectronic structure and the manufacture of the microelectronic structure. Specifically, the disclosure relates to an interconnect barrier layer between a rhodium contact structure and a copper interconnect structure in a microelectronic structure. The microelectronic structure provides for low resistance in microelectronic devices.Type: GrantFiled: March 24, 2008Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: John M. Cotte, Balasubramanian Haran, Christopher C. Parks, Xiaoyan Shao, Eva E. Simonyi
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Publication number: 20100123205Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.Type: ApplicationFiled: November 17, 2008Publication date: May 20, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
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Publication number: 20090239062Abstract: The present disclosure relates to a microelectronic structure and the manufacture of the microelectronic structure. Specifically, the disclosure relates to an interconnect barrier layer between a rhodium contact structure and a copper interconnect structure in a microelectronic structure. The microelectronic structure provides for low resistance in microelectronic devices.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Inventors: John M. Cotte, Balasubramanian Haran, Christopher C. Parks, Xiaoyan Shao, Eva E. Simonyi
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Patent number: 7585765Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.Type: GrantFiled: August 15, 2007Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Nancy R. Klymko, Christopher C. Parks, Keith Kwong Hon Wong
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Patent number: 7276796Abstract: An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.Type: GrantFiled: March 15, 2006Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Nancy R. Klymko, Christopher C. Parks, Keith Kwong Hon Wong
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Patent number: 7227265Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 ?m and via openings filled with electroplated copper than is substantially free of internal seams or voids.Type: GrantFiled: March 29, 2004Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton