Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Abstract: An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Abstract: A buffer and synchronization circuit for a computer system which provides synchronization of the column address strobe (CAS) signals provided to the memory DRAMs and which interlocks the memory data latch enable with the CAS signals provided from the memory controller without adding extra clock cycles or wait states. A synchronized buffer circuit receives the CAS signals from the memory controller and provides a plurality of synchronized duplicate CAS signals to the memory DRAMs. The synchronized buffer circuit includes several gate drivers in a single semiconductor chip so that each of the drivers has approximately the same delay in order to minimize skew between the duplicated CAS signals. An interlocking buffer circuit receives the memory data latch enable signal and the CAS signals from the memory controller and provides a synchronized memory latch enable to the data buffers.

Abstract: A computer system which includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.