Patents by Inventor Christopher Chamberland
Christopher Chamberland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12169673Abstract: A Toffoli magic state to be injected in preparation of a Toffoli gate may be prepared using a bottom-up approach. In the bottom-up approach, computational basis states are prepared in a fault tolerant manner using a STOP algorithm. The computational basis states are further used to prepare the Toffoli magic state. The STOP algorithm tracks syndrome outcomes and can be used to determine when to stop repeating syndrome measurements such that faults are guaranteed to be below a threshold level. Also, the STOP algorithm may be used in growing repetition code from a first code distance to a second code distance, such as for use in the computational basis states.Type: GrantFiled: October 7, 2022Date of Patent: December 17, 2024Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Fernando Brandao, Earl Campbell
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Patent number: 12165013Abstract: Techniques for training local decoders for use in a local and global decoding scheme for quantum error correction of circuit-level noise within quantum surface codes such that the decoding schemes have fast decoding throughout and low latency times for quantum algorithms are disclosed. The local decoders may have a neural network architecture and may be trained using training data sets comprising simulated rounds of syndrome measurements for respective simulated quantum surface codes in addition to information such as syndrome differences, qubit placements, and temporal boundaries within the simulated rounds of syndrome measurements in order to train the local decoders for arbitrarily sized quantum surface codes and arbitrary numbers of rounds of syndrome measurements. Following a local decoding stage in which a large number of data errors have been corrected by a local decoder, error correction for remaining errors may continue with a more efficient global decoding stage.Type: GrantFiled: September 30, 2022Date of Patent: December 10, 2024Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Luis Goncalves, Prasahnt Sivarajah, Eric Christopher Peterson, Sebastian Johannes Grimberg
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Patent number: 12165006Abstract: A technique for performing lattice surgery without using twists is disclosed. Also, an error correcting code and decoder is provided that allows for error decoding of Pauli measurements performed in association with a lattice surgery operation. This allows for overall run-times of lattice surgery to be reduced. For example, some level of errors are tolerable, because they can be corrected, thus fewer measurement rounds (dm) may be performed for a given round of Pauli measurements. Additionally, a temporal encoding of lattice surgery technique is provided, which may additionally or alternatively be used to shorten run times. Also, a quantum computer layout is provided, wherein the layout includes a core computing region and a cache region. Also, protocols for swapping logical qubits between the core and cache are provided.Type: GrantFiled: December 8, 2021Date of Patent: December 10, 2024Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Earl Terence Campbell
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Publication number: 20240386304Abstract: High-fidelity measurements of qubits are achieved by increasing a number of measurements taken by use of a swap operation and a readout qubit, deflating a bosonic qubit for which measurement outcomes are affected by single photon/phonon loss events, deflating a bosonic qubit enabling readout in other basis, and evolving the qubit under a Hamiltonian that couples a mode to be measured to another mode where the Hamiltonian is selected from a three wave mixing interaction, and/or a combination of these techniques.Type: ApplicationFiled: July 23, 2024Publication date: November 21, 2024Applicant: Amazon Technologies, Inc.Inventors: Harald Esko Jakob Putterman, Kyungjoo Noh, Christopher Chamberland, Amir Safavi-Naeini, Oskar Jon Painter, Patricio Arrangoiz Arriola
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Patent number: 12093789Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.Type: GrantFiled: January 13, 2023Date of Patent: September 17, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew W. Cross, Christopher Chamberland, Jay M. Gambetta, Jared B. Hertzberg, Theodore J. Yoder, Guanyu Zhu
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Patent number: 12093785Abstract: High-fidelity measurements of qubits are achieved by increasing a number of measurements taken by use of a swap operation and a readout qubit, deflating a bosonic qubit for which measurement outcomes are affected by single photon/phonon loss events, deflating a bosonic qubit enabling readout in other basis, and evolving the qubit under a Hamiltonian that couples a mode to be measured to another mode where the Hamiltonian is selected from a three wave mixing interaction, and/or a combination of these techniques.Type: GrantFiled: November 13, 2020Date of Patent: September 17, 2024Assignee: Amazon Technologies, Inc.Inventors: Harald Esko Jakob Putterman, Kyungjoo Noh, Christopher Chamberland, Amir Safavi-Naeini, Oskar Jon Painter, Patricio Arrangoiz Arriola
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Patent number: 12057859Abstract: Techniques for implementing a local neural network and global decoding scheme for quantum error correction of circuit-level noise within quantum surface codes such that the decoding schemes have fast decoding throughout and low latency times for quantum algorithms are disclosed. A local neural network decoder may be pre-trained via a supervised learning technique such that the local neural network decoder may be applied for error correction in the presence of circuit-level noise in arbitrarily sized surface codes in a local decoding stage. Prior to a global decoding stage, an intermediate stage may be used to remove vertical pairs of highlighted vertices within the matching graph, which may reduce a syndrome density within the matching graph to allow for faster decoding at the global decoding stage. Such an intermediate stage may include application of a syndrome collapse or vertical cleanup technique.Type: GrantFiled: September 30, 2022Date of Patent: August 6, 2024Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Luis Goncalves, Prasahnt Sivarajah, Eric Christopher Peterson, Sebastian Johannes Grimberg
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Patent number: 12008438Abstract: A technique for performing lattice surgery using twists is disclosed. Also, an error correcting code and decoder is provided that allows for error decoding of Pauli measurements performed in association with a lattice surgery operation. This allows for overall run-times of lattice surgery to be reduced. For example, some level of errors are tolerable, because they can be corrected, thus fewer measurement rounds (dm) may be performed for a given round of Pauli measurements. Additionally, a temporal encoding of lattice surgery technique is provided, which may additionally or alternatively be used to shorten run times. Also, a quantum computer layout is provided, wherein the layout includes a core computing region and a cache region. Also, protocols for swapping logical qubits between the core and cache are provided.Type: GrantFiled: March 29, 2022Date of Patent: June 11, 2024Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Earl Campbell
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Patent number: 12007835Abstract: Techniques for performing temporally encoded lattice surgery (TELS) protocols to reduce space-time costs of lattice surgery measurements are disclosed. A given quantum algorithm may be represented using Pauli-based computation, and associated multi-qubit Pauli operators may be encoded into codewords of a given classical error-correcting code. A hybrid error detection and correction scheme may then be applied during a given TELS protocol in which classical error syndromes corresponding to errors with weights up to a certain weight limit may be corrected while other classical error syndromes corresponding to errors with higher weights may cause given lattice surgery measurements to be remeasured. The weight limit for the hybrid scheme may be chosen based, at least in part, on a number of codewords used, a size of a parallelizable Pauli set used to represent the quantum algorithm, and a distance parameter of the chosen classical error-correcting code.Type: GrantFiled: December 12, 2022Date of Patent: June 11, 2024Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Prithviraj Prabhu
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Patent number: 11983601Abstract: A hybrid Bacon-Shor surface code is implemented using a fault tolerant quantum computer comprising hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit. The hybrid Bacon-Shor surface code only couples four phononic modes per given ATS, reducing cross-talk as compared to other systems that couple more phononic modes per ATS. Also, measurements are performed such that three parity measurements are taken between a phononic readout mode and a transmon qubit in a given syndrome measurement cycle.Type: GrantFiled: March 30, 2021Date of Patent: May 14, 2024Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Kyungjoo Noh
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Patent number: 11966817Abstract: A technique for merging, via lattice surgery, a color code and a surface code, and subsequentially decoding one or more rounds of stabilizer measurements of the merged code is disclosed. Such a technique can be applied to bottom-up fault-tolerant magic state preparation protocol such that an encoded magic state can be teleported from a color code to a surface code. Decoding the stabilizer measurements of the merged code requires a decoding algorithm specific to the merged code in which error correction involving qubits at the border between the surface and color code portions of the merged code is performed. Error correction involving qubits within the surface code portion and within color code portion, respectively, may additionally be performed. In some cases, the magic state is prepared in a color code via a technique for encoding a Clifford circuit design problem as an SMT decision problem.Type: GrantFiled: March 14, 2022Date of Patent: April 23, 2024Assignee: Amazon Technologies, Inc.Inventors: Noah John Shutty, Christopher Chamberland
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Patent number: 11941483Abstract: A fault tolerant quantum computer is implementing using hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit, wherein the open transmission line is configured to absorb photons from a dump mode of the control circuit. Filters are included in the control circuit to suppress cross-talk errors. Additionally, frequencies and pump mode detunings for respective multiplexed control circuits are strategically selected to reduce cross-talk errors.Type: GrantFiled: March 30, 2021Date of Patent: March 26, 2024Assignee: Amazon Technologies, Inc.Inventors: Connor Hann, Kyungjoo Noh, Patricio Arrangoiz Arriola, Christopher Chamberland, Fernando Brandao
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Patent number: 11900221Abstract: A technique for performing lattice surgery without using twists is disclosed. Also, an error correcting code and decoder is provided that allows for error decoding of Pauli measurements performed in association with a lattice surgery operation. This allows for overall run-times of lattice surgery to be reduced. For example, some level of errors are tolerable, because they can be corrected, thus fewer measurement rounds (dm) may be performed for a given round of Pauli measurements. Additionally, a temporal encoding of lattice surgery technique is provided, which may additionally or alternatively be used to shorten run times. Also, a quantum computer layout is provided, wherein the layout includes a core computing region and a cache region. Also, protocols for swapping logical qubits between the core and cache are provided.Type: GrantFiled: December 8, 2021Date of Patent: February 13, 2024Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Earl Terence Campbell
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Patent number: 11853159Abstract: A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information is further used to determine confidence values for error corrected measurements from the GKP qubits of the surface code. These confidence values are used to dynamically determine edge weights in a matching graph used to decode syndrome measurements of the surface code, wherein the confidence values are obtained using a maximum-likelihood decoding protocol for two-qubit gates. Space-time correlated edges and other edges are included in the matching graph and weighted based at least in part on confidence values for qubits forming the respective edges.Type: GrantFiled: June 29, 2021Date of Patent: December 26, 2023Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Kyungjoo Noh, Fernando Brandao
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Patent number: 11741279Abstract: A top-down distillation process for preparing low-error rate Toffoli gates utilizes Toffoli magic states as inputs to the distillation process. Multiple Toffoli magic states are used to distill a low-error rate Toffoli gate via one round of distillation. Lattice surgery operations are performed to distill the low-error rate Toffoli gate from the multiple Toffoli magic states. Each round of lattice surgery operations acts on a check qubit associated with the low error rate Toffoli gate being distilled. Errors introduced during the distillation (if non-trivial) will be manifest in the check qubit. Thus, the check qubit is measured subsequent to performing the lattice surgery operations to verify that the distilled Toffoli gate is very likely to be provide a correct result.Type: GrantFiled: November 13, 2020Date of Patent: August 29, 2023Assignee: Amazon Technologies, Inc.Inventors: Earl Campbell, Christopher Chamberland
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Publication number: 20230205622Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.Type: ApplicationFiled: January 13, 2023Publication date: June 29, 2023Inventors: Andrew W. Cross, Christopher Chamberland, Jay M. Gambetta, Jared B. Hertzberg, Theodore J. Yoder, Guanyu Zhu
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Preparation of qunaught states for a surface GKP code using a three (or higher) level ancilla system
Patent number: 11645570Abstract: A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information is further used to determine confidence values for error corrected measurements from the GKP qubits of the surface code. These confidence values are used to dynamically determine edge weights in a matching graph used to decode syndrome measurements of the surface code, wherein the confidence values are obtained using a maximum-likelihood decoding protocol for two-qubit gates. Also, a three-level ancilla is used to more reliably squeeze the GKP qunaught states.Type: GrantFiled: June 29, 2021Date of Patent: May 9, 2023Assignee: Amazon Technologies, Inc.Inventors: Kyungjoo Noh, Christopher Chamberland, Fernando Brandao -
Publication number: 20230080126Abstract: A Toffoli magic state to be injected in preparation of a Toffoli gate may be prepared using a bottom-up approach. In the bottom-up approach, computational basis states are prepared in a fault tolerant manner using a STOP algorithm. The computational basis states are further used to prepare the Toffoli magic state. The STOP algorithm tracks syndrome outcomes and can be used to determine when to stop repeating syndrome measurements such that faults are guaranteed to be below a threshold level. Also, the STOP algorithm may be used in growing repetition code from a first code distance to a second code distance, such as for use in the computational basis states.Type: ApplicationFiled: October 7, 2022Publication date: March 16, 2023Applicant: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Fernando Brandao, Earl Campbell
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Patent number: 11599820Abstract: A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information may further be used to determine confidence values for error corrected measurements from the GKP qubits of the surface code.Type: GrantFiled: June 29, 2021Date of Patent: March 7, 2023Assignee: Amazon Technologies, Inc.Inventors: Kyungjoo Noh, Christopher Chamberland, Fernando Brandao
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Patent number: 11580436Abstract: Extra edges are added to a group of edges for use in decoding syndrome measurements of a surface code implemented using hybrid acoustic-electric qubits. The extra edges include two-dimensional cross-edges and three-dimensional space-time correlated edges that identify correlated errors arising from spurious photon dissipation processes of a multiplexed control circuit that leads to cross-talk between storage modes of a set of the mechanical resonators controlled by the given multiplexed control circuit. Additionally, error probabilities used for edge weighting incorporate error probabilities due to the spurious photon dissipation processes.Type: GrantFiled: March 30, 2021Date of Patent: February 14, 2023Assignee: Amazon Technologies, Inc.Inventors: Christopher Chamberland, Kyungjoo Noh, Connor Hann, Fernando Brandao