Patents by Inventor Christopher Chamberland

Christopher Chamberland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11983601
    Abstract: A hybrid Bacon-Shor surface code is implemented using a fault tolerant quantum computer comprising hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit. The hybrid Bacon-Shor surface code only couples four phononic modes per given ATS, reducing cross-talk as compared to other systems that couple more phononic modes per ATS. Also, measurements are performed such that three parity measurements are taken between a phononic readout mode and a transmon qubit in a given syndrome measurement cycle.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 14, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Kyungjoo Noh
  • Patent number: 11966817
    Abstract: A technique for merging, via lattice surgery, a color code and a surface code, and subsequentially decoding one or more rounds of stabilizer measurements of the merged code is disclosed. Such a technique can be applied to bottom-up fault-tolerant magic state preparation protocol such that an encoded magic state can be teleported from a color code to a surface code. Decoding the stabilizer measurements of the merged code requires a decoding algorithm specific to the merged code in which error correction involving qubits at the border between the surface and color code portions of the merged code is performed. Error correction involving qubits within the surface code portion and within color code portion, respectively, may additionally be performed. In some cases, the magic state is prepared in a color code via a technique for encoding a Clifford circuit design problem as an SMT decision problem.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: April 23, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Noah John Shutty, Christopher Chamberland
  • Patent number: 11941483
    Abstract: A fault tolerant quantum computer is implementing using hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit, wherein the open transmission line is configured to absorb photons from a dump mode of the control circuit. Filters are included in the control circuit to suppress cross-talk errors. Additionally, frequencies and pump mode detunings for respective multiplexed control circuits are strategically selected to reduce cross-talk errors.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Connor Hann, Kyungjoo Noh, Patricio Arrangoiz Arriola, Christopher Chamberland, Fernando Brandao
  • Patent number: 11900221
    Abstract: A technique for performing lattice surgery without using twists is disclosed. Also, an error correcting code and decoder is provided that allows for error decoding of Pauli measurements performed in association with a lattice surgery operation. This allows for overall run-times of lattice surgery to be reduced. For example, some level of errors are tolerable, because they can be corrected, thus fewer measurement rounds (dm) may be performed for a given round of Pauli measurements. Additionally, a temporal encoding of lattice surgery technique is provided, which may additionally or alternatively be used to shorten run times. Also, a quantum computer layout is provided, wherein the layout includes a core computing region and a cache region. Also, protocols for swapping logical qubits between the core and cache are provided.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 13, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Earl Terence Campbell
  • Patent number: 11853159
    Abstract: A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information is further used to determine confidence values for error corrected measurements from the GKP qubits of the surface code. These confidence values are used to dynamically determine edge weights in a matching graph used to decode syndrome measurements of the surface code, wherein the confidence values are obtained using a maximum-likelihood decoding protocol for two-qubit gates. Space-time correlated edges and other edges are included in the matching graph and weighted based at least in part on confidence values for qubits forming the respective edges.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 26, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Kyungjoo Noh, Fernando Brandao
  • Patent number: 11741279
    Abstract: A top-down distillation process for preparing low-error rate Toffoli gates utilizes Toffoli magic states as inputs to the distillation process. Multiple Toffoli magic states are used to distill a low-error rate Toffoli gate via one round of distillation. Lattice surgery operations are performed to distill the low-error rate Toffoli gate from the multiple Toffoli magic states. Each round of lattice surgery operations acts on a check qubit associated with the low error rate Toffoli gate being distilled. Errors introduced during the distillation (if non-trivial) will be manifest in the check qubit. Thus, the check qubit is measured subsequent to performing the lattice surgery operations to verify that the distilled Toffoli gate is very likely to be provide a correct result.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 29, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Earl Campbell, Christopher Chamberland
  • Publication number: 20230205622
    Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
    Type: Application
    Filed: January 13, 2023
    Publication date: June 29, 2023
    Inventors: Andrew W. Cross, Christopher Chamberland, Jay M. Gambetta, Jared B. Hertzberg, Theodore J. Yoder, Guanyu Zhu
  • Patent number: 11645570
    Abstract: A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information is further used to determine confidence values for error corrected measurements from the GKP qubits of the surface code. These confidence values are used to dynamically determine edge weights in a matching graph used to decode syndrome measurements of the surface code, wherein the confidence values are obtained using a maximum-likelihood decoding protocol for two-qubit gates. Also, a three-level ancilla is used to more reliably squeeze the GKP qunaught states.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: May 9, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Kyungjoo Noh, Christopher Chamberland, Fernando Brandao
  • Publication number: 20230080126
    Abstract: A Toffoli magic state to be injected in preparation of a Toffoli gate may be prepared using a bottom-up approach. In the bottom-up approach, computational basis states are prepared in a fault tolerant manner using a STOP algorithm. The computational basis states are further used to prepare the Toffoli magic state. The STOP algorithm tracks syndrome outcomes and can be used to determine when to stop repeating syndrome measurements such that faults are guaranteed to be below a threshold level. Also, the STOP algorithm may be used in growing repetition code from a first code distance to a second code distance, such as for use in the computational basis states.
    Type: Application
    Filed: October 7, 2022
    Publication date: March 16, 2023
    Applicant: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Fernando Brandao, Earl Campbell
  • Patent number: 11599820
    Abstract: A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information may further be used to determine confidence values for error corrected measurements from the GKP qubits of the surface code.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: March 7, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Kyungjoo Noh, Christopher Chamberland, Fernando Brandao
  • Patent number: 11580436
    Abstract: Extra edges are added to a group of edges for use in decoding syndrome measurements of a surface code implemented using hybrid acoustic-electric qubits. The extra edges include two-dimensional cross-edges and three-dimensional space-time correlated edges that identify correlated errors arising from spurious photon dissipation processes of a multiplexed control circuit that leads to cross-talk between storage modes of a set of the mechanical resonators controlled by the given multiplexed control circuit. Additionally, error probabilities used for edge weighting incorporate error probabilities due to the spurious photon dissipation processes.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: February 14, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Kyungjoo Noh, Connor Hann, Fernando Brandao
  • Patent number: 11556411
    Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Andrew W. Cross, Christopher Chamberland, Jay M. Gambetta, Jared B. Hertzberg, Theodore J. Yoder, Guanyu Zhu
  • Publication number: 20220327410
    Abstract: A hybrid Bacon-Shor surface code is implemented using a fault tolerant quantum computer comprising hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit. The hybrid Bacon-Shor surface code only couples four phononic modes per given ATS, reducing cross-talk as compared to other systems that couple more phononic modes per ATS. Also, measurements are performed such that three parity measurements are taken between a phononic readout mode and a transmon qubit in a given syndrome measurement cycle.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 13, 2022
    Applicant: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Kyungjoo Noh
  • Patent number: 11468219
    Abstract: A Toffoli magic state to be injected in preparation of a Toffoli gate may be prepared using a bottom-up approach. In the bottom-up approach, computational basis states are prepared in a fault tolerant manner using a STOP algorithm. The computational basis states are further used to prepare the Toffoli magic state. The STOP algorithm tracks syndrome outcomes and can be used to determine when to stop repeating syndrome measurements such that faults are guaranteed to be below a threshold level. Also, the STOP algorithm may be used in growing repetition code from a first code distance to a second code distance, such as for use in the computational basis states.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 11, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Fernando Brandao, Earl Campbell
  • Patent number: 11455207
    Abstract: A method of error correction for a quantum computer includes identifying each of a plurality of physical qubits arranged in a lattice pattern over a surface in a quantum processor of the quantum computer as a one of a data qubit, an ancilla qubit or a flag qubit to define a plurality of data qubits, ancilla qubits and flag qubits. Each pair of interacting data qubits interact with a flag qubit and adjacent flag qubits both interact with a common ancilla qubit. The method further includes performing measurements of weight-four stabilizers, weight-two stabilizers, or both of a surface code formed using at least a sub-plurality of the plurality of physical qubits, or performing measurements of weight-four Bacon-Shor type gauge operators; and correcting fault-tolerantly quantum errors in one or more of the at least sub-plurality of physical qubits based on a measurement from at least one flag qubit.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Christopher Chamberland, Guanyu Zhu, Theodore James Yoder, Andrew W. Cross
  • Patent number: 11449783
    Abstract: Techniques regarding encoding a quantum circuit to a trivalent lattice scheme to identify flag qubit outcomes are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a graph component that can encode a quantum circuit to a trivalent lattice that maps an ancilla qubit to a plurality of data qubits via a plurality of flag qubits based on a connectivity scheme of the quantum circuit.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 20, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher Chamberland, Theodore James Yoder, Andrew W. Cross, Guanyu Zhu
  • Publication number: 20220180236
    Abstract: A fault tolerant quantum computer is implementing using hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit, wherein the open transmission line is configured to absorb photons from a dump mode of the control circuit. Filters are included in the control circuit to suppress cross-talk errors. Additionally, frequencies and pump mode detunings for respective multiplexed control circuits are strategically selected to reduce cross-talk errors.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 9, 2022
    Applicant: Amazon Technologies, Inc.
    Inventors: Connor Hann, Kyungjoo Noh, Patricio Arrangoiz Arriola, Christopher Chamberland, Fernando Brandao
  • Publication number: 20220178995
    Abstract: Extra edges are added to a group of edges for use in decoding syndrome measurements of a surface code implemented using hybrid acoustic-electric qubits. The extra edges include two-dimensional cross-edges and three-dimensional space-time correlated edges that identify correlated errors arising from spurious photon dissipation processes of a multiplexed control circuit that leads to cross-talk between storage modes of a set of the mechanical resonators controlled by the given multiplexed control circuit. Additionally, error probabilities used for edge weighting incorporate error probabilities due to the spurious photon dissipation processes.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 9, 2022
    Applicant: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Kyungjoo Noh, Connor Hann, Fernando Brandao
  • Publication number: 20220156621
    Abstract: A fault tolerant quantum computer is implemented using hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites excite phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit, wherein the open transmission line is configured to absorb photons from a dump mode of the control circuit.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: Amazon Technologies, Inc.
    Inventors: Patricio Arrangoiz Arriola, Amir Safavi-Naeini, Oskar Jon Painter, Connor Hann, Fernando Brandao, Kyungjoo Noh, Joseph Kramer Iverson, Harald Esko Jakob Putterman, Christopher Chamberland, Earl Campbell
  • Publication number: 20220156441
    Abstract: A top-down distillation process for preparing low-error rate Toffoli gates utilizes Toffoli magic states as inputs to the distillation process. Multiple Toffoli magic states are used to distill a low-error rate Toffoli gate via one round of distillation. Lattice surgery operations are performed to distill the low-error rate Toffoli gate from the multiple Toffoli magic states. Each round of lattice surgery operations acts on a check qubit associated with the low error rate Toffoli gate being distilled. Errors introduced during the distillation (if non-trivial) will be manifest in the check qubit. Thus, the check qubit is measured subsequent to performing the lattice surgery operations to verify that the distilled Toffoli gate is very likely to be provide a correct result.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: Amazon Technologies, Inc.
    Inventors: Earl Campbell, Christopher Chamberland