Abstract: A method of forming a part includes 3D printing a photopolymerizable resin and forming a preformed part and subsequently post-curing the preformed part with electron beams. The preformed part may be cured via UV curing. A section of the preformed part post-cured with electron beams may have a thickness of at least 1.0 centimeter, for example, at least 2.0 centimeters or at least 3.0 centimeters. An electron beam dosage to post-cure the preformed part may be between 10 kilogray (kGy) and 100 kGy. The preformed part may be 3D printed using stereolithography (SLA), digital light processing (DLP) or material jetting (MJ) and the photopolymerizable resin may include at least one of an acrylate functional polymer and a methacrylate functional polymer. In the alternative, or in addition to, the photopolymerizable resin may include at least one of a urethane, a polyester, and a polyether.

Abstract: A transitional treatment composition and methods of treating coal refuse are provided. The transitional treatment composition comprises an anionic acrylate-acrylamide copolymer having from about 30 mole percent to about 50 mole percent (meth)acrylate, from about 50 mole percent to about 70 mole percent (meth)acrylamide, and a reduced specific viscosity of from about 18 dL/g to about 30 dL/g. The transitional treatment composition can be made down in an aqueous liquid.

Abstract: A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

Abstract: A semiconductor device includes a base structure including a first interlayer dielectric (ILD) layer and a contact including a conductive liner disposed along a conductive core, a conductive plug disposed on the conductive liner between the conductive core and the first ILD layer to a height of the base structure, and a metallization level including a conductive line and a self-aligned via underneath the conductive line disposed on the contact and the conductive plug. The conductive plug protects underlying material and increases connectivity between the self-aligned via and the contact that was reduced due to misalignment.

Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

Abstract: Interconnect structures and methods for forming the interconnect structures generally include forming a bulk metal encapsulated in first and second interlayer dielectrics, a liner layer about a lower surface of the bulk metal and a metal cap layer about an upper surface of the bulk metal. The liner layer is in the first interlayer dielectric and the metal cap layer is in the second interlayer dielectric, wherein liner layer and the metal cap layer are different metals.

Abstract: A method and apparatus for establishing unsolicited block acknowledgements is provided. During a process, at a first wireless device, to associate with a basic service set that includes a second wireless communication device, the first wireless device transmits, via a controller and using a radio: an indication that the first wireless communication device supports block acknowledgements; and at least one common block acknowledgement parameter defining unsolicited block acknowledgement. Thereafter, the first wireless communication device exchanges data with the second wireless communication device according to the at least one common block acknowledgement parameter defining the unsolicited block acknowledgement.

Abstract: An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: A video stream management system includes a video controller that live renders video. Moreover, the video stream management system also includes a display that is communicatively coupled to the video controller and displays a primary video feed that includes the live rendered video. The video controller, the display, or a combination thereof, embeds a pixel pattern in the primary video feed. Additionally, the video feed management system monitors one or more displayed images on the display to identify an error in the primary video feed.

Abstract: Aspects of this invention, inter alia, relate to novel systems for targeting, editing or manipulating DNA in a cell, using novel synthetic RNA-guided nucleases (sRGNs). The sRGNs are derived from wildtype or parental small type II CRISPR Cas9 endonucleases.

Abstract: A biopsy and therapy device comprising: a needling unit for holding and inserting a biopsy needle; an imaging module comprising an ultrasound probe and an actuator for moving the probe in a reciprocal action; a first arcuate slide; a second arcuate slide in sliding engagement with the first arcuate slide and a linkage to which the first arcuate slide is mounted; said linkage arranged to move the first and second arcuate slides within a vertical plane; said needling unit mounted to said arcuate slide wherein the first and second arcuate slides are mounted perpendicular to each other so as to rotate the needling unit about respective first and second principal axes.

Abstract: Described herein are methods of purifying polynucleotides, e.g., imRNA and oligonucleotides, e.g., probes, primers and siRNA, using monolithic columns with immobilized ligands coupled to the monolithic column. Also described are monolithic columns for purifying polynucleotides from a sample; and methods of preparing such columns.

Abstract: A system for coordinating valet services comprises a server including a server controller, a server database in communication with the controller, and server memory in communication with the controller, the server memory storing server program instructions that are executable by the controller. The system also includes a customer mobile device and a valet mobile device associated with a customer application and a valet application, respectively. The customer application is associated with a vehicle identifier, and the valet application is associated with a valet identifier. In response to receipt of the valet identifier and the vehicle identifier by the server from the customer application, the server controller prompts the valet application to request a ticket number.

Abstract: A biopsy and therapy device comprising: a needling unit for holding and inserting a biopsy needle; an imaging module comprising an ultrasound probe and an actuator for moving the probe in a reciprocal action; a first arcuate slide; a second arcuate slide in sliding engagement with the first arcuate slide and a linkage to which the first arcuate slide is mounted; said linkage arranged to move the first and second arcuate slides within a vertical plane; said needling unit mounted to said arcuate slide wherein the first and second arcuate slides are mounted perpendicular to each other so as to rotate the needling unit about respective first and second principal axes.

Abstract: A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.

Abstract: An input circuit is provided for coupling to a source-synchronous multi-level bus carrying data, clock, and complementary clock signals. The clock and complementary clock signals have a less than full voltage swing than the data signal so they can act as reference voltages for the data signal. The circuit includes a first differential receiver having inputs coupled to the data and the clock signals, a second differential receiver having inputs coupled to the data signal and a reference signal, and a third differential receiver having inputs coupled to the data and the complementary clock signals. The circuit further includes first, second, and third flip-flops having data inputs coupled to outputs of the first, the second, and the third differential receivers, and clock inputs coupled to a delayed clock signal generated from the clock and the complementary clock signals. The outputs of the flip-flops determine the level of the data signal.

Abstract: A method is provided to align clock and data signals over a source-synchronous link. The method includes sending header data and a default clock signal over the link. The header indicates a start of a training packet and the default clock signal ensures that the header is received without error. The method further includes providing a long clock pulse, phase shifting the clock signal during the long clock pulse, and thereafter sending training data and the clock signal over the link. The above steps are repeated until the training data are received with error. At that point, the phase shift of the clock signal is saved as a boundary of an optimal alignment. The above steps are then repeated with the clock signal shifted in a different direction. Once another boundary is located, the boundary midpoint is saved as the phase shift that provides the optimal alignment.

Abstract: A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.

Abstract: A method for a mix mode driver to accommodate traces of different lengths includes sequentially shifting values of a data signal to a number of stages and sequentially amplifying the values of the data signal at least one stage. Depending on the length of trace for the data signal, the method further includes providing at least one amplifying coefficient to at least one stage and coupling a subset of the stages to an adder. The method finally includes outputting the data signal from the adder to the trace.

Abstract: A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.