Patents by Inventor Christopher D. Sheraw
Christopher D. Sheraw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10991689Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.Type: GrantFiled: April 5, 2019Date of Patent: April 27, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Abu Naser M. Zainuddin, Christopher D. Sheraw, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala S Haran
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Publication number: 20200321332Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.Type: ApplicationFiled: April 5, 2019Publication date: October 8, 2020Inventors: Abu Naser M. Zainuddin, Christopher D. Sheraw, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala S. Haran
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Patent number: 10396078Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.Type: GrantFiled: June 7, 2018Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
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Publication number: 20180286863Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.Type: ApplicationFiled: June 7, 2018Publication date: October 4, 2018Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
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Patent number: 10020307Abstract: The disclosure is directed to an integrated circuit structure and a method of forming the same. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner lining the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer.Type: GrantFiled: February 10, 2017Date of Patent: July 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Matthew W. Stoker, Mira Park, George R. Mulfinger, Yinxiao Yang
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Patent number: 9953873Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: GrantFiled: May 24, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Publication number: 20170345719Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: ApplicationFiled: May 24, 2016Publication date: November 30, 2017Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Patent number: 9634084Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.Type: GrantFiled: February 10, 2016Date of Patent: April 25, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Christopher D. Sheraw, Chengwen Pei, Eric T. Harley, Yue Ke, Henry K. Utomo, Yinxiao Yang, Zhibin Ren
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Patent number: 9287399Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: October 7, 2014Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Publication number: 20150084096Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: October 7, 2014Publication date: March 26, 2015Inventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 8940595Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: March 15, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Publication number: 20140264558Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 8497212Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.Type: GrantFiled: February 28, 2011Date of Patent: July 30, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Katherina E. Babich, Alessandro C. Callegari, Christopher D. Sheraw, Eugene J. O'Sullivan
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Publication number: 20120217590Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.Type: ApplicationFiled: February 28, 2011Publication date: August 30, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Katherina E. Babich, Alessandro C. Callegari, Christopher D. Sheraw, Eugene J. O'Sullivan
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Patent number: 7956417Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: GrantFiled: July 20, 2010Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
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Patent number: 7911024Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: GrantFiled: February 17, 2010Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
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Patent number: 7893493Abstract: An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.Type: GrantFiled: July 10, 2006Date of Patent: February 22, 2011Assignees: International Business Machines Corproation, Advanced Micro Devices, Inc.Inventors: Yun-Yu Wang, Linda Black, Judson R. Holt, Woo-Hyeong Lee, Scott Luning, Christopher D. Sheraw
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Patent number: 7871893Abstract: Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.Type: GrantFiled: January 28, 2008Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Christopher D. Sheraw, Richard Wise
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Publication number: 20100283089Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: ApplicationFiled: July 20, 2010Publication date: November 11, 2010Applicants: International Business Machines Corporation, GLOBAL FOUNDRIES, INC.Inventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
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Patent number: 7820501Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: GrantFiled: October 11, 2006Date of Patent: October 26, 2010Assignees: International Business Machines Corporation, GlobalFoundries, IncInventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried