Abstract: Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level during high speed operation and may provide their output signals at relatively lower voltage levels that are less than the overdrive voltage during low power operation.

Abstract: Integrated circuits with backside power delivery capabilities are provided. An integrated circuit may include a substrate having front and back surfaces, a first interconnect stack formed on the front surface, and a second interconnect stack formed on the back surface. Routing structures that carry data signals, control signals, and other user signals may be formed only in the first interconnect stack. A large majority of routing structures that carry power supply signals may be formed in the second interconnect stack. Decoupling capacitor circuitry such as deep trench capacitors may be formed in the back surface of the substrate. The integrated circuit may be mounted on a package substrate. The first interconnect stack may be coupled to the package substrate via wire bond pads, whereas the second interconnect stack may be coupled to the package substrate via an array of solder bumps.

Abstract: An integrated circuit is disclosed. The integrated circuit may include an interface circuit region and logic circuitry region. The interface circuit region includes interface circuits that transfers signals in and out of the integrated circuit. The logic circuitry region includes logic circuitry that is configured to implement a logic function. The logic circuitry region surrounds the interface circuit region from at least two sides, from at least three sides, or from all four sides.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: Techniques and mechanisms for providing embedded Input/Output (IO) blocks in a floor plan of a semiconductor device are provided, where the embedded IO blocks constitute partial columns (i.e., they do not extend from the bottom through to the top of the semiconductor device). In some embodiments, the partial column IO banks are skewed away from one another. In some embodiments, the partial column IO banks are located away from the center of the semiconductor device. Techniques and mechanisms for implementing symmetrical package routing using skewed partial column IO banks are also provided.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: Integrated circuits such as programmable logic devices are provided that have circuit blocks such as memory blocks. The integrated circuits may be tested to determine whether the circuit blocks contain defects. If defective circuitry is identified, switching circuitry in the circuit blocks can be configured to switch redundant circuitry into use. Repairs may be made by loading repair data into fuses on the integrated circuit. Each circuit block may have an associated control circuit with a unique address. A master block repair controller may be used to route repair data to each control circuit over a shared bus using the unique addresses of the control circuits. Each control circuit may have register circuitry into which addresses and repair data are loaded. Testing circuitry may be used to supply test signals. Multiplexing circuitry can selectively route either the test signals or repair data to the control circuits over the shared bus.

Abstract: A programmable logic device (PLD) having minimal leakage current for inactive logic blocks is provided. The PLD includes an array of logic blocks. Among the array of logic blocks, one of the array of logic blocks monitors the level of activity of each of the remaining logic blocks. The level of activity may be monitored by observing the input and output pin of the logic blocks. The PLD further includes a plurality of driven wires defining a routing pattern between the array of logic blocks. When one of the array of logic blocks detect inactivity in any one of the remaining logic blocks for a certain duration, the one of the array logic blocks transmits a signal invoking a sleep mode for the inactive logic blocks. A sleep transistor with a threshold voltage level that is capable minimizing the leakage current is associated with each of the remaining block. The gate of the sleep transistor receives the signal transmitted by one of the array logic blocks and the signal switches off the sleep transistor.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.