Patents by Inventor Christopher J. Berry
Christopher J. Berry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11932360Abstract: A tuned mass damper (TMD) system in combination with a floating offshore wind turbine (FOWT) platform includes a barge type FOWT platform having a hull configured to have a wind turbine tower mounted thereon. A TMD system is mounted in the hull and has a first TMD configured to operate at a first frequency, and a second TMD configured to operate at a second frequency different than the first frequency.Type: GrantFiled: November 4, 2019Date of Patent: March 19, 2024Assignee: University of Maine System Board of TrusteesInventors: Christopher K. Allen, Anthony M. Viselli, Andrew J. Goupee, Habib J. Dagher, Robert E. Berry, Jeffrey L. Lindner, Frederick S. Gant, John S. Townsend, Rebecca L. Williams
-
Patent number: 11621243Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: GrantFiled: October 26, 2020Date of Patent: April 4, 2023Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
-
Patent number: 11157586Abstract: A computer-implemented method, computer program product, and computing system is provided for scoping searches within a website. In an implementation, a method may receiving a search request. The method may also include identifying a location of a search scoping feature within a website hierarchy. The method may further include setting a search scope relative to the search request based on, at least in part, the location of the search scoping feature.Type: GrantFiled: October 20, 2017Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Mark C. Hampton
-
Publication number: 20210111151Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: ApplicationFiled: October 26, 2020Publication date: April 15, 2021Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
-
Patent number: 10818637Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: GrantFiled: March 25, 2019Date of Patent: October 27, 2020Assignee: Amkor Technology, Inc.Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
-
Publication number: 20190348395Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: ApplicationFiled: March 25, 2019Publication date: November 14, 2019Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
-
Patent number: 10372866Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.Type: GrantFiled: February 13, 2017Date of Patent: August 6, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Adam R. Jatkowski, Frank Malgioglio, Ryan M. Nett, Joseph J. Palumbo, Sean Salisbury, Gerald L. Strevig, III
-
Patent number: 10242966Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.Type: GrantFiled: July 14, 2017Date of Patent: March 26, 2019Assignee: Amkor Technology, Inc.Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
-
Patent number: 10229238Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.Type: GrantFiled: October 31, 2016Date of Patent: March 12, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Lakshmi Reddy, Sourav Saha
-
Patent number: 10157255Abstract: A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.Type: GrantFiled: November 28, 2017Date of Patent: December 18, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew D. Affeldt, Christopher J. Berry, Randall J. Darden, Shyam Ramji, Eddy St. Juste
-
Patent number: 10140414Abstract: A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.Type: GrantFiled: April 5, 2016Date of Patent: November 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: George Antony, Christopher J. Berry, Ricardo H. Nigaglioni, Sridhar H. Rangarajan, Sourav Saha, Vinay K. Singh
-
Publication number: 20180232481Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.Type: ApplicationFiled: February 13, 2017Publication date: August 16, 2018Inventors: Christopher J. Berry, Adam R. Jatkowski, Frank Malgioglio, Ryan M. Nett, Joseph J. Palumbo, Sean Salisbury, Gerald L. Strevig, III
-
Patent number: 9934341Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.Type: GrantFiled: November 11, 2015Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Chris A. Cavitt, Adam P. Matheny, Jose L. Neves, Jesse P. Surprise, Michael H. Wood
-
Patent number: 9928322Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.Type: GrantFiled: April 22, 2016Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Chris A. Cavitt, Adam P. Matheny, Jose L. Neves, Jesse P. Surprise, Michael H. Wood
-
Publication number: 20180082008Abstract: A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.Type: ApplicationFiled: November 28, 2017Publication date: March 22, 2018Inventors: Matthew D. Affeldt, Christopher J. Berry, Randall J. Darden, Shyam Ramji, Eddy St. Juste
-
Patent number: 9910952Abstract: A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.Type: GrantFiled: June 30, 2016Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew D. Affeldt, Christopher J. Berry, Randall J. Darden, Shyam Ramji, Eddy St. Juste
-
Publication number: 20180060447Abstract: A computer-implemented method, computer program product, and computing system is provided for scoping searches within a website. In an implementation, a method may receiving a search request. The method may also include identifying a location of a search scoping feature within a website hierarchy. The method may further include setting a search scope relative to the search request based on, at least in part, the location of the search scoping feature.Type: ApplicationFiled: October 20, 2017Publication date: March 1, 2018Inventors: Christopher J. Berry, Mark C. Hampton
-
Patent number: 9881100Abstract: A computer-implemented method, computer program product, and computing system is provided for scoping searches within a website. In an implementation, a method may receiving a search request. The method may also include identifying a location of a search scoping feature within a website hierarchy. The method may further include setting a search scope relative to the search request based on, at least in part, the location of the search scoping feature.Type: GrantFiled: January 14, 2013Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Christopher J. Berry, Mark C. Hampton
-
Patent number: 9875980Abstract: Methods for copper pillar protection may include forming a metal post over a contact on a semiconductor die, where the metal post comprises a sidewall. A metal cap may be formed on the metal post and may be wider than the width of the metal post. A solder bump may be formed on the metal cap, and a conformal passivation layer may be formed on at least the sidewall of the metal post. The metal cap may be rounded shaped or rectangular shaped in cross-section. The metal post and the metal cap may comprise copper. The metal cap may comprise a copper layer and a nickel layer. The seed metal layer may comprise one or more of titanium, tungsten, and copper. The conformal passivation layer may comprise a nonwettable polymer. Horizontal portions of the conformal passivation layer may be removed utilizing an anisotropic etch such as a plasma etch.Type: GrantFiled: May 23, 2014Date of Patent: January 23, 2018Assignee: AMKOR TECHNOLOGY, INC.Inventors: Glenn Rinne, Dean Zehnder, Christopher J. Berry, Robert Lanzone, Ludovico Bancod
-
Publication number: 20180004885Abstract: A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Matthew D. Affeldt, Christopher J. Berry, Randall J. Darden, Shyam Ramji, Eddy St. Juste