Abstract: A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.

Abstract: An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.

Abstract: Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design. The components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities.

Abstract: A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The methods is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors.

Abstract: A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.

Abstract: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

Abstract: Novel strains of isolated and purified bacteria have been identified which have the ability to degrade petroleum hydrocarbons including a variety of PAHs. Several isolates also exhibit the ability to produce a biosurfactant. The combination of the biosurfactant-producing ability along with the ability to degrade PAHs enhances the efficiency with which PAHs may be degraded. Additionally, the biosurfactant also provides an additional ability to bind heavy metal ions for removal from a soil or aquatic environment.

Abstract: A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to its original net list state while keeping the routing solution.

Abstract: Novel strains of isolated and purified bacteria have been identified which have the ability to degrade petroleum hydrocarbons including a variety of PAHs. Several isolates also exhibit the ability to produce a biosurfactant. The combination of the biosurfactant-producing ability along with the ability to degrade PAHs enhances the efficiency with which PAHs may be degraded. Additionally, the biosurfactant also provides an additional ability to bind heavy metal ions for removal from a soil or aquatic environment.

Abstract: Novel strains of isolated and purified bacteria have been identified which have the ability to degrade petroleum hydrocarbons including a variety of PAHs. Several isolates also exhibit the ability to produce a biosurfactant. The combination of the biosurfactant-producing ability along with the ability to degrade PAHs enhances the efficiency with which PAHs may be degraded. Additionally, the biosurfactant also provides an additional ability to bind heavy metal ions for removal from a soil or aquatic environment.

Abstract: A semiconductor device has a substrate having a plurality of metal layers. A die is coupled to the substrate. A plurality of metal wires is provided. At least one end of each of the metal wires is electrically coupled to at least one metal layer. A mold compound is used to encapsulate the die, a first surface of the substrate, and the plurality of metal wires. A portion of at least one metal wire remains exposed. A conductive coating is applied to the mold compound and to the portion of the at least one metal wire exposed.

Abstract: A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.

Abstract: An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.

Abstract: A sensor package has a substrate. A sensor die having an inactive surface is bonded to the substrate. An active surface of the sensor die is exposed. A portion of the active surface of the sensor die has an active imaging area. A metal bezel is formed on the active surface of the sensor die and separate from the imaging area.

Abstract: An interconnect structure (i.e., a laminate interposer) which is mounted to a semiconductor package leadframe or substrate prior to molding the package body of the semiconductor package. During the molding process, the top of the laminate interposer is protected such that the top surface of the interposer is exposed subsequent to the completion of the molding process. In this manner, electrical signals can be routed from the package leadframe or substrate to the top surface of the package body of the semiconductor package. Subsequently, a mating package can be mounted on top of the underlying package by way of a ball grid array (BGA) interconnect or other type of interconnect.

Abstract: A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.

Abstract: A circuit element package has a substrate having a plurality of electrically conductive patterns, a die pad, and an access hole formed through the die pad and substrate. A plurality of leads is coupled to the substrate. A circuit element die is attached to the die pad wherein a first sensor port is positioned over the access hole. A die attach membrane is provided for attaching the circuit element die to the die pad. The die attach membrane allows the circuit element die to sense ambient while protecting the circuit element die from environmental damage. An encapsulant is used for covering portions of the circuit element die.

Abstract: The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.

Abstract: A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.

Abstract: A semiconductor device has a substrate comprising at least one dielectric layer and at least one metal layer on a first surface of the substrate. A die is attached to the first surface of the substrate. A mold compound is used to encapsulate the die and partially encapsulate the first surface of the substrate. The mold compound has a protrusion proximate to the at least one metal layer. A conductive material covers the mold compound, including the protrusion, and contacts the at least one metal layer.