Abstract: A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.

Abstract: Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets.

Abstract: In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.

Abstract: An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.

Abstract: A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

Abstract: A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.

Abstract: A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to it's original net list state while keeping the routing solution.

Abstract: Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design. The components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities.

Abstract: The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

Abstract: A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The methods is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors.

Abstract: A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either Strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported, Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.

Abstract: In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.

Abstract: A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

Abstract: Novel strains of isolated and purified bacteria have been identified which have the ability to degrade petroleum hydrocarbons including a variety of PAHs. Several isolates also exhibit the ability to produce a biosurfactant. The combination of the biosurfactant-producing ability along with the ability to degrade PAHs enhances the efficiency with which PAHs may be degraded. Additionally, the biosurfactant also provides an additional ability to bind heavy metal ions for removal from a soil or aquatic environment.

Abstract: A method of microbial enhanced oil recovery for recovering oil from an oil-bearing rock formation is provided. The methodology uses a consortium of bacteria including a mixture of surfactant producing bacteria and non-surfactant enzyme producing bacteria which may release hydrocarbons from bitumen containing sands. The described bioprocess can work with existing petroleum recovery protocols. The consortium microorganisms are also useful for treatment of above oil sands, ground waste tailings, subsurface oil recovery, and similar materials to enhance remediation and/or recovery of additional hydrocarbons from the materials.

Abstract: In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.

Abstract: A method of performing tie net routing within an integrated circuit chip is disclosed without using wiring. Due to repeated use of designs in modern chip, there are often unused portions of the design that need to be connected permanently to a local logical1 or logical 0. These connections, known as tie nets, are not timing critical signals that, when poorly implemented can get in the way of functional signals in an integrated circuit. The current method is to connect the pin to the nearest power connections of the correct polarity. This requires some amount of wiring resources that may be needed for other functions or pin access. Accordingly, the present invention avoids this situation by avoiding wiring.

Abstract: This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.

Abstract: In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access

Abstract: A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.