Patents by Inventor Christopher K. Morzano
Christopher K. Morzano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6727739Abstract: A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plurality of delay elements and a minimum and maximum delay boundary. According to an embodiment of the invention, an artificial minimum or maximum boundary, or both, is established on the delay line such that during initialization of the delay locked loop circuit, the circuit cannot lock on a delay element beyond the artificial minimum or maximum boundaries. By offsetting the artificial minimum and maximum boundaries from the actual minimum and maximum boundaries of the delay line, a buffer of delay elements is established at the actual delay line boundaries.Type: GrantFiled: January 22, 2002Date of Patent: April 27, 2004Assignee: Micron Technology, Inc.Inventors: Eric T. Stubbs, Christopher K. Morzano
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Publication number: 20040037135Abstract: A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide column select signals that are indicative of a column address in the memory cell array, and uses the column address to perform a column redundancy check. The data communication circuit latches data signals that are associated with the write command in response to a data strobe signal. The control circuit causes the addressing circuit to perform the column redundancy check during a delay to accommodate variations in the timing of the data strobe signal and begins providing the column select signals to the memory cell array after performing the column redundancy check. The memory device may be a double data rate (DDR) synchronous dynamic random access memory (SDRAM), for example.Type: ApplicationFiled: August 28, 2003Publication date: February 26, 2004Inventor: Christopher K. Morzano
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Patent number: 6691214Abstract: A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.Type: GrantFiled: August 29, 2000Date of Patent: February 10, 2004Assignee: Micron Technology, Inc.Inventors: Wen Li, Christopher K. Morzano
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Patent number: 6643194Abstract: A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., x16 or x32.Type: GrantFiled: August 19, 2002Date of Patent: November 4, 2003Assignee: Micron Technology, Inc.Inventors: Kevin J. Ryan, Christopher K. Morzano, Wen Li
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Patent number: 6636093Abstract: A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plurality of delay elements and a minimum and maximum delay boundary. According to an embodiment of the invention, an artificial minimum or maximum boundary, or both, is established on the delay line such that during initialization of the delay locked loop circuit, the circuit cannot lock on a delay element beyond the artificial minimum or maximum boundaries. By offsetting the artificial minimum and maximum boundaries from the actual minimum and maximum boundaries of the delay line, a buffer of delay elements is established at the actual delay line boundaries.Type: GrantFiled: July 14, 2000Date of Patent: October 21, 2003Assignee: Micron Technology, Inc.Inventors: Eric T. Stubbs, Christopher K. Morzano
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Patent number: 6633503Abstract: A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transition logic circuit to a midpoint voltage. As the node of the transition logic circuit starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from rail to rail as before.Type: GrantFiled: July 31, 2001Date of Patent: October 14, 2003Assignee: Micron Technology, Inc.Inventor: Christopher K. Morzano
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Patent number: 6615331Abstract: A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide column select signals that are indicative of a column address in the memory cell array, and uses the column address to perform a column redundancy check. The data communication circuit latches data signals that are associated with the write command in response to a data strobe signal. The control circuit causes the addressing circuit to perform the column redundancy check during a delay to accommodate variations in the timing of the data strobe signal and begins providing the column select signals to the memory cell array after performing the column redundancy check. The memory device may be a double data rate (DDR) synchronous dynamic random access memory (SDRAM), for example.Type: GrantFiled: February 22, 2000Date of Patent: September 2, 2003Assignee: Micron Technology, Inc.Inventor: Christopher K. Morzano
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Patent number: 6600691Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.Type: GrantFiled: July 29, 2002Date of Patent: July 29, 2003Assignee: Micron Technology, Inc.Inventors: Christopher K. Morzano, Wen Li
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Patent number: 6556494Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.Type: GrantFiled: March 14, 2001Date of Patent: April 29, 2003Assignee: Micron Technology, Inc.Inventors: Christopher K. Morzano, Wen Li
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Patent number: 6532180Abstract: A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., ×16 or ×32.Type: GrantFiled: June 20, 2001Date of Patent: March 11, 2003Assignee: Micron Technology, Inc.Inventors: Kevin J. Ryan, Christopher K. Morzano, Wen Li
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Publication number: 20020196675Abstract: A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is preempted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., ×16 or ×32.Type: ApplicationFiled: June 20, 2001Publication date: December 26, 2002Inventors: Kevin J. Ryan, Christopher K. Morzano, Wen Li
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Publication number: 20020196700Abstract: A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., x16 or x32.Type: ApplicationFiled: August 19, 2002Publication date: December 26, 2002Inventors: Kevin J. Ryan, Christopher K. Morzano, Wen Li
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Publication number: 20020186608Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.Type: ApplicationFiled: July 29, 2002Publication date: December 12, 2002Applicant: Micron Technology, Inc.Inventors: Christopher K. Morzano, Wen Li
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Publication number: 20020169922Abstract: A number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Addressing of the row or redundant row in a memory array of a memory device may be accomplished by using a calibration fuse bank to address a row or a redundant row of the memory array, by using a fuse bank of the memory device to address a redundant row of the memory array, or by storing the row address of a row in a memory controller and providing the row address to the memory device during calibration. A redundant row used for calibration may be a redundant row not utilized by a memory device during repair of its memory array. A row used for calibration may be a row not utilized by a memory device due to the nature of the specific application in which that memory device is being used. A unique data pattern may then be written to and read from the addressed row or redundant row for read/write timing calibration.Type: ApplicationFiled: May 8, 2001Publication date: November 14, 2002Inventors: Mark R. Thomann, Christopher K. Morzano, Wen Li
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Publication number: 20020131313Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.Type: ApplicationFiled: March 14, 2001Publication date: September 19, 2002Applicant: Micron Technology, Inc.Inventors: Christopher K. Morzano, Wen Li
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Patent number: 6446180Abstract: A memory device includes a data array, array control logic, a delay locked loop circuit, timing control logic, and a first storage device. The array control logic is adapted to receive a read command synchronized with an external clock signal and to read at least a first data element from the data array based on the read command. The delay locked loop circuit is adapted to receive the external clock signal and delay the external clock signal by a programmable amount to generate a delay locked loop clock signal. The timing control logic is adapted to generate a first input enable signal based on the external clock signal and a first output enable signal based on the delay locked loop clock signal. The first storage device adapted to receive the first data element. The first storage device has an input terminal enabled in response to the first input enable signal and an output terminal enabled in response to the first output enable signal.Type: GrantFiled: July 30, 2001Date of Patent: September 3, 2002Assignee: Micron Technology, Inc.Inventors: Wen Li, Christopher K. Morzano
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Publication number: 20020089361Abstract: A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plurality of delay elements and a minimum and maximum delay boundary. According to an embodiment of the invention, an artificial minimum or maximum boundary, or both, is established on the delay line such that during initialization of the delay locked loop circuit, the circuit cannot lock on a delay element beyond the artificial minimum or maximum boundaries. By offsetting the artificial minimum and maximum boundaries from the actual minimum and maximum boundaries of the delay line, a buffer of delay elements is established at the actual delay line boundaries.Type: ApplicationFiled: January 22, 2002Publication date: July 11, 2002Inventors: Eric T. Stubbs, Christopher K. Morzano
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Patent number: 6392453Abstract: An integrated differential buffer circuit and its method of operation are described in which the buffer circuit has an internal bias line for controlling the supply of voltage to the buffer circuit. When the buffer circuit is first enabled, a start voltage is initially applied to the bias line and then removed to ensure proper operation of the buffer circuit when first enabled.Type: GrantFiled: June 20, 2001Date of Patent: May 21, 2002Assignee: Micron Technology, Inc.Inventors: Christopher K. Morzano, Mark R. Thomann
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Patent number: 6385108Abstract: A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transition logic circuit to a midpoint voltage. As the node of the transition logic circuit starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from rail to rail as before.Type: GrantFiled: December 15, 2000Date of Patent: May 7, 2002Assignee: Micron Technology, Inc.Inventor: Christopher K. Morzano
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Publication number: 20010046169Abstract: A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transition logic circuit to a midpoint voltage. As the node of the transition logic circuit starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from rail to rail as before.Type: ApplicationFiled: July 31, 2001Publication date: November 29, 2001Inventor: Christopher K. Morzano